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參數(shù)資料
| 型號： | ADAV4601BSTZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 8/60頁 |
| 文件大小： | 0K |
| 描述： | IC AUDIO CODEC PROCESSOR 80-LQFP |
| 標準包裝： | 1 |
| 系列： | SigmaDSP® |
| 類型： | 音頻處理器 |
| 應用： | TV |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 80-LQFP |
| 供應商設備封裝： | 80-LQFP（14x14） |
| 包裝： | 托盤 |
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ADAV4601
Rev. B | Page 16 of 60
SCL
Serial clock for the I2C control port. SCL features a glitch
elimination filter that removes spurious pulses that are
less than 50 ns wide.
MUTE
Mute input request. This active-low input pin controls the
muting of the output ports (both analog and digital) from the
ADAV4601. When low, it asserts mute on the outputs that are
enabled in the audio flow.
RESET
Active-low reset signal. After RESET goes high, the circuit blocks
are powered down. The blocks can be individually powered up
with software. When the part is powered up, it takes approximately
3072 internal clocks to initialize the internal circuitry. The internal
system clock is equal to MCLKI until the PLL is powered and
enabled, after which the internal system clock becomes 2560 × fS
(122.88 MHz). When the PLL is powered up and enabled after
reset, it takes approximately 3 ms to lock. When the audio
processor is enabled, it takes approximately 32,768 internal system
clocks to initialize and load the default flow to the audio processor
memory. The audio processor is not available during this time.
AUXIN1L AND AUXIN1R
Analog inputs to the on-chip ADCs.
AUXOUT1L, AUXOUT1R, AUXOUT3L, AUXOUT3R,
AUXOUT4L, and AUXOUT4R
Auxiliary DAC analog outputs. These pins can be programmed
to supply the outputs of the internal audio processing for line
out or record use.
HPOUT1L and HPOUT1R
Analog outputs from the headphone amplifiers.
PLL_LF
PLL loop filter connection. A 100 nF capacitor and a 2 kΩ resistor
in parallel with a 1 nF capacitor tied to AVDD are required for
the PLL loop filter to operate correctly.
VREF
Voltage reference for DACs and ADCs. This pin is driven by an
internal 1.5 V reference voltage.
FILTA and FILTD
Decoupling nodes for the ADC and DAC. Decoupling
capacitors should be connected between these nodes and
AGND, typically 47 μF in parallel with 0.1 μF and 10 μF in
parallel with 0.1 μF, respectively.
PWM1A, PWM1B, PWM2A, PWM2B, PWM3A, PWM3B,
PWM4A, and PWM4B
Differential pulse-width modulation outputs are suitable for
driving Class-D amplifiers.
PWM_READY
This pin is set high when PWM is enabled and stable.
AVDD
Analog power supply pins. These pins should be connected
to 3.3 V. Each AVDD pin should be decoupled with a 0.1 μF
capacitor to AGND, as close to the pin as possible. In addition,
the ADC supply (Pin 4) and the DAC supplies (Pin 68 and Pin 71)
should share a 10 μF capacitor to ground. The PLL supply (Pin 53)
should have an additional 1 nF and 10 μF capacitor to ground,
and the headphone supply (Pin 59) should have an additional
10 μF capacitor to ground.
DVDD
Digital power supply pins. These pins should be connected to a 1.8 V
digital supply. For optimal performance, each DVDD/DGND
pair requires a 0.1 μF decoupling capacitor as close to the pin as
possible. In addition, these 0.1 μF decoupling capacitors are in
parallel with a single 10 μF capacitor.
ODVDD
Digital interface power supply pin. Connect this pin to a 3.3 V
digital supply. Decouple this pin with 10 μF and 0.1 μF capacitors to
DGND, as close to the pin as possible.
DGND
Digital ground.
AGND
Analog ground.
ODGND
Ground for the digital interface power supply.
ISET
ADC current setting resistor. See the ADC Inputs section for
more details.
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