參數(shù)資料
型號： ADAV4601BSTZ
廠商： Analog Devices Inc
文件頁數(shù)： 48/60頁
文件大?。?/td> 0K
描述： IC AUDIO CODEC PROCESSOR 80-LQFP
標(biāo)準(zhǔn)包裝： 1
系列： SigmaDSP®
類型： 音頻處理器
應(yīng)用： TV
安裝類型： 表面貼裝
封裝/外殼： 80-LQFP
供應(yīng)商設(shè)備封裝： 80-LQFP（14x14）
包裝： 托盤
ADAV4601
Rev. B | Page 52 of 60
Address 0x000A Misc Control Register (Default: 0x0800)
Table 51.
Bit No.
Bit Name
Description
Default
Bit[15]
PWM ready flag (read-only)
Indicates the current status of the PWM ready pin. When PWM ready is low, the
PWM is not enabled. When PWM ready is high, the PWM is enabled and stable.
0
0b = PWM ready pin low
1b = PWM ready pin high
Bit[14]
Enable selected PWM channels
When enabled, all PWM channels selected by Bits[10:7] can be used.
0
0b = all PWM channels disabled
1b = selected PWM channels enabled
Bit[13]
MCLK_OUT CLK type select
Used to configure the MCLK_OUT pin.
0
0b = crystal frequency on MCLK_OUT
1b = internally generated clocks on MCLK_OUT
Bit[12]
PWM enable/disable patterns
Enables the enable/disable patterns for the PWM block.
0
0b = enable/disable pattern not used
1b = use enable/disable pattern
Bit[11]
DAC mod offset
Adds dc offset to the DAC Σ-Δ modulator to eliminate idle tones. It is recommended
that this bit be disabled before the ADC/DAC engine is powered up in
Control Register 0x0007[1].
1
0b = enabled
1b = disabled
Bit[10]
PWM Enable 4
The PWM outputs are disabled by default, which means that the outputs are
at GND. When this bit is set to 1 and Bit[14] of this register is set to 1, then the
PWM Enable 4 channel is enabled.
0
0b = disabled
1b = enabled
Bit[9]
PWM Enable 3
The PWM outputs are disabled by default, which means that the outputs are
at GND. When this bit is set to 1 and Bit[14] of this register is set to 1, then the
PWM Enable 3 channel is enabled.
0
0b = disabled
1b = enabled
Bit[8]
PWM Enable 2
The PWM outputs are disabled by default, which means that the outputs are
at GND. When this bit is set to 1 and Bit[14] of this register is set to 1, then the
PWM Enable 2 channel is enabled.
0
0b = disabled
1b = enabled
Bit[7]
PWM Enable 1
The PWM outputs are disabled by default, which means that the outputs are
at GND. When this bit is set to 1 and Bit[14] of this register is set to 1, then the
PWM Enable 1 channel is enabled.
0
0b = disabled
1b = enabled
Bit[6]
SRC2 lock (read-only)
Set to 1 when the sample rate converter (SRC) locks to the incoming data,
indicating the data is valid.
0
0b = not locked
1b = locked
Bit[5]
SRC1 lock (read-only)
Set to 1 when the sample rate converter (SRC) locks to the incoming data,
indicating the data is valid.
0
0b = not locked
1b = locked
Bit[4]
MCLK_OUT enable
Enables the clock chosen by Bit[13] and Bits[3:1] to be output on the MCLK_OUT pin.
0
0b = MCLK_OUT function disabled
1b = MCLK_OUT function enabled
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