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參數(shù)資料
| 型號： | ADAV4601BSTZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 11/60頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC AUDIO CODEC PROCESSOR 80-LQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | SigmaDSP® |
| 類型： | 音頻處理器 |
| 應(yīng)用： | TV |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 80-LQFP |
| 供應(yīng)商設(shè)備封裝： | 80-LQFP（14x14） |
| 包裝： | 托盤 |
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ADAV4601
Rev. B | Page 19 of 60
R/W
00
1
0
1
0
00
1
0
1
0
ADR
SEL
ADR
SEL
SCL
(CONTINUED)
SDA
(CONTINUED)
SCL
(CONTINUED)
SDA
(CONTINUED)
SDA
FRAME 1
CHIP ADDRESS BYTE
START BY
MASTER
ACK BY
ADAV4601
ACK BY
ADAV4601
FRAME 2
SUBADDRESS BYTE 1
FRAME 3
SUBADDRESS BYTE 2
ACK BY
ADAV4601
REPEATED
START BY
MASTER
ACK BY
ADAV4601
FRAME 4
CHIP ADDRESS BYTE
FRAME 5
READ DATA BYTE 1
ACK BY
MASTER
ACK BY
MASTER
FRAME 6
READ DATA BYTE 1
STOP BY
MASTER
07
0-
10
2
Figure 24. I2C Read Format
I2C READ AND WRITE OPERATIONS
ADC INPUTS
Table 6 shows the timing of a single word write operation.
Every ninth clock, the ADAV4601 issues an acknowledge by
pulling SDA low.
The ADAV4601 has two ADC inputs. By default, this is configured
as a single stereo input; however, because the audio processor is
programmable, these inputs can be reconfigured.
Table 7 shows the timing of the burst mode write sequence.
Table 7 shows an example where the target destination registers
are two bytes. The ADAV4601 auto-increments its subaddress
register counter every two bytes until a stop condition occurs.
The ADC inputs are shown in Figure 25. The analog inputs are
current inputs (100 μA rms FS) with a 1.5 V dc bias voltage. Any
input voltage can be accommodated by choosing a suitable
combination of input resistor (RIN) and ISET resistor (RISET)
using the formulas
The timing of a single word read operation is shown in Table 8.
Note that the first R/W bit is still 0, indicating a write operation.
This is because the subaddress must be written to set up the
internal address. After the ADAV4601 acknowledges the receipt
of the subaddress, the master must issue a repeated start command
followed by the chip address byte with the R/W set to 1 (read).
The ADAV4601 responds with the read result on SDA. The
master then responds every ninth clock with an acknowledge
pulse to the ADAV4601.
RIN
= VFS rms/100 μA rms
RISET = 2RIN
/VIN
Resistor matching (typically 1%) between RIN and RISET is
important to ensure a full-scale signal on the ADC without
clipping. A 10 μF dc blocking capacitor is also required at the input.
After reset, the ADCs are in a power-down state. The ADCs can
be powered up using the global power-up in the initialization
control register (0x0000). In power critical applications, it is
possible to use the analog power management register (0x0005)
to power-up or power-down individual ADCs.
Table 9 shows the timing of the burst mode read sequence.
Table 9 shows an example where the target read registers are two
bytes. The ADAV4601 increments its subaddress register every two
bytes because the requested subaddress corresponds to a register or
memory area with word lengths of two bytes. Other address
ranges may have a variety of word lengths ranging from one to six
bytes; the ADAV4601 always decodes the subaddress and sets
the auto-increment circuit so that the address increments after the
appropriate number of bytes.
DC BIAS
1.5V
24-BIT
ADC
20k
ANALOG INPUT
100A rms
FULL SCALE
DC BIAS
1.5V
24-BIT
ADC
20k
ANALOG INPUT
100A rms
FULL SCALE
AUXIN1L
AUXIN1R
RISET
20k
+
10F
+
10F
07
0-
1
03
Figure 25. Analog Input Section
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