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參數(shù)資料
| 型號： | ADAV4601BSTZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 10/60頁 |
| 文件大小： | 0K |
| 描述： | IC AUDIO CODEC PROCESSOR 80-LQFP |
| 標準包裝： | 1 |
| 系列： | SigmaDSP® |
| 類型： | 音頻處理器 |
| 應用： | TV |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 80-LQFP |
| 供應商設備封裝： | 80-LQFP（14x14） |
| 包裝： | 托盤 |
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ADAV4601
Rev. B | Page 18 of 60
Table 6. Single Word I2C Write1
S
Chip address,
R/W = 0
AS
Subaddress high
AS
Subaddress low
AS
Data Byte 1
AS
Data Byte 2
…
AS
Data Byte N
P
1 S = start bit, P = stop bit, and AS = acknowledge by slave.
Table 7. Burst Mode I2C Write1
S
Chip
address,
R/W = 0
AS
Subaddress
high
AS
Subaddress
low
AS
Data-Word 1,
Byte 1
AS
Data-Word 1,
Byte 2
AS
Data-Word 2,
Byte 1
AS
Data-Word 2,
Byte 2
AS
…
P
1 S = start bit, P = stop bit, and AS = acknowledge by slave.
Table 8. Single Word I2C Read1
S
Chip address,
R/W = 0
AS
Subaddress
high
AS
Subaddress
low
AS
S
Chip address,
R/W = 1
AS
Data Byte 1
AM
Data
Byte 2
…
AM
Data
Byte N
P
1 S = start bit, P = stop bit, AM = acknowledge by master, and AS = acknowledge by slave.
Table 9. Burst Mode I2C Read1
S
Chip address,
R/W = 0
AS
Subaddress
high
AS
Subaddress
low
AS
S
Chip address,
R/W = 1
AS
Data-Word 1
Byte 1
AM
Data-Word 1
Byte 2
AM
…
P
1 S = start bit, P = stop bit, AM = acknowledge by master, and AS = acknowledge by slave.
R/W
0
SCL
(CONTINUED)
SDA
(CONTINUED)
SDA
0
1
0
ADR
SEL
1
0
FRAME 1
CHIP ADDRESS BYTE
START BY
MASTER
ACK BY
ADAV4601
ACK BY
ADAV4601
FRAME 2
SUBADDRESS BYTE 1
FRAME 2
SUBADDRESS BYTE 2
ACK BY
ADAV4601
ACK BY
ADAV4601
STOP BY
MASTER
07
0-
1
01
FRAME 3
DATA BYTE 1
Figure 23. I2C Write Format
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