參數(shù)資料
型號(hào)： ADAV4601BSTZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 7/60頁(yè)
文件大小： 0K
描述： IC AUDIO CODEC PROCESSOR 80-LQFP
標(biāo)準(zhǔn)包裝： 1
系列： SigmaDSP®
類型： 音頻處理器
應(yīng)用： TV
安裝類型： 表面貼裝
封裝/外殼： 80-LQFP
供應(yīng)商設(shè)備封裝： 80-LQFP（14x14）
包裝： 托盤
ADAV4601
Rev. B | Page 15 of 60
PIN FUNCTIONS
DETAILED PIN DESCRIPTIONS
Table 5 shows the pin numbers, mnemonics, and descriptions
for the ADAV4601. The input pins have a logic threshold
compatible with 3.3 V input levels.
SDIN0, SDIN1, SDIN2, and SDIN3/SPDIF_IN0
Serial data inputs. These input pins provide the digital audio
data to the signal processing core. Any of the inputs can be
routed to either of the SRCs for conversion; this input is then
not available as a synchronous input to the audio processor but
only as an input through the selected SRC. The serial format for
the synchronous data is selected by Bits[3:2] of the Serial Port
Control Register 1. If the SRCs are required, the serial format is
selected by Bits[12:9] of the same register. The synchronous inputs
are capable of using any pair of serial clocks, LRCLK0/BCLK0,
LRCLK1/BCLK1, or LRCLK2/BCLK2. By default, they use
LRCLK1 and BCLK1. See Figure 26 for more details regarding
the configuration of the synchronous inputs.
SDIN3 is a shared pin with SPDIF_IN0. If SDIN3 is not in use, this
pin can be used to connect an S/PDIF signal from an external
source, such as an MPEG decoder, to the ADAV4601 on-chip
S/PDIF output multiplexer. If SPDIF_OUT is selected from one
of the SPDIF_IN (external) signals, the signal is simply passed
through from input to output.
LRCLK0/SPDIF_IN1, BCLK0/SPDIF_IN2,
LRCLK1/SPDIF_IN3, BCLK1/SPDIF_IN4,
LRCLK2/SPDIF_IN5, and BCLK2/SPDIF_IN6
By default, LRCLK1 and BCLK1 are associated with the
synchronous inputs, LRCLK0 and BCLK0 are associated with
SRC1, and LRCLK2 and BCLK2 are associated with SRC2.
However, the SRCs and synchronous inputs can use any of
the serial clocks (see Figure 26). LRCLK0, BCLK0, LRCLK1,
BCLK1, LRCLK2, and BCLK2 are shared pins with SPDIF_IN1,
SPDIF_IN2, SPDIF_IN3, SPDIF_IN4, SPDIF_IN5, and
SPDIF_IN6, respectively. If LRCLK0/LRCLK1/ LRCLK2 or
BCLK0/BCLK1/BCLK2 are not in use, these pins can be used
to connect an S/PDIF signal from an external source, such as an
MPEG decoder, to the ADAV4601 on-chip S/PDIF output
multiplexer. If SPDIF_OUT is selected from one of the SPDIF_IN
(external) signals, the signal is simply passed through from input
to output.
SDO0/AD0
Serial data output. This pin can output two channels of digital
audio using a variety of standard 2-channel formats. The clocks
for SDO0 are always the same as those used by the synchronous
inputs; therefore, LRCLK1 and BCLK1 are used by default,
although SDO0 is capable of using any pair of serial clocks,
LRCLK0/BCLK0, LRCLK1/BCLK1, or LRCLK2/BCLK2.
The Serial Port Control Register 1 selects the serial format for the
synchronous output. On reset, the SDO0 pin duplicates as the
I2C address select pin. In this mode, the logical state of the pin
is polled for four MCLKI cycles following reset. The address
select bit is set as the majority poll of the logic level of the pin after
the four MCLKI cycles.
SPDIF_OUT/SDO1
The ADAV4601 contains an S/PDIF multiplexer functionality that
allows the SPDIF_OUT signal to be chosen from an internally
generated S/PDIF signal or from the S/PDIF signal of an external
source, which is connected via one of the SPDIF_IN pins. This pin
can also be configured as an additional serial output (SDO1) as an
alternate function.
MCLKI/XIN
Master clock input. The ADAV4601 uses a PLL to generate the
appropriate internal clock for the audio processing core. A clock
signal of a suitable frequency can be connected directly to this pin,
or a crystal can be connected between MCLKI/XIN and XOUT
together with the appropriate capacitors to DGND to generate
a suitable clock signal.
XOUT
This pin is used in conjunction with MCLKI/XIN to generate a
clock signal for the ADAV4601.
MCLK_OUT
This pin can be used to output MCLKI or one of the internal
system clocks. Note that the output level of this pin is referenced to
DVDD (1.8 V) and not ODVDD (3.3 V) like all the other digital
inputs and outputs.
SDA
Serial data input for the I2C control port. SDA features a glitch
elimination filter that removes spurious pulses that are less than
50 ns wide.
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