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| 型號： | ADAV4601BSTZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 21/60頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC AUDIO CODEC PROCESSOR 80-LQFP |
| 標準包裝： | 1 |
| 系列： | SigmaDSP® |
| 類型： | 音頻處理器 |
| 應(yīng)用： | TV |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 80-LQFP |
| 供應(yīng)商設(shè)備封裝： | 80-LQFP（14x14） |
| 包裝： | 托盤 |
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ADAV4601
Rev. B | Page 28 of 60
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Constant Time Update
A constant time update is calculated by adding a step value that
is determined after each target is loaded. The equation for this
step size is
Step = (Target Data Slew Data)/(Number of Steps)
Figure 44 shows a plot of the target/slew RAM operating in
constant time mode. For this example, 128 steps are used to reach
the target value. This type of ramping takes a fixed amount of time
for a given number of steps, regardless of the difference in the
initial state and the target value. Figure 45 shows a plot of a
constant time ramp from 80 dB to 6 dB (half scale) using
128 steps; therefore, the ramp takes the same amount of time
as the previous ramp from 80 dB to 0 dB. A constant time
decreasing ramp plot is shown in Figure 46.
0
Figure 46. Slew RAM—Constant Time Update Decreasing Ramp, Full Scale
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LAYOUT RECOMMENDATIONS
Parts Placement
The priority for decoupling is VREF, FILTA, FILTD, PLL_LF, and
finally the supplies. For effective decoupling in all cases, make sure
the decoupling capacitor sees the respective ground pin before the
ground plane.
0
The 1 nF and 100 nF bypass capacitors for the PLL loop filter
should be placed as close as possible to the ADAV4601. All 10 μF
and 0.1 μF bypass capacitors, which are recommended for every
analog, digital, and power/ground pair, should also be placed as
close as possible to the ADAV4601 with priority given to the 0.1 μF
capacitor.
The ADC input voltage-to-current resistors and the ADC
current set resistor should be placed as close as possible to the
respective pins.
Figure 44. Slew RAM—Constant Time Update Increasing Ramp, Full Scale
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Crystal Oscillator Circuit
All traces in the crystal oscillator circuit (see Figure 22) should be
kept as short as possible to minimize stray capacitance. In addition,
avoid long board traces connected to any of these components
because such traces may affect crystal startup and operation.
PWM Outputs
All PWM output differential pairs should be matched in length,
that is, PWM1A = PWM1B, PWM2A = PWM2B.
Grounding
30
A split ground plane should be used in the layout of the ADAV4601
with the analog and digital grounds connected underneath the
ADAV4601 using a single link. This layout is to avoid possible
ground loop currents in the analog and digital ground planes.
Components in the analog signal path should be placed away
from the digital signals. No signal traces should cross the gap
between the planes.
Figure 45. Slew RAM—Constant Time Update Increasing Ramp, Half Scale
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