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參數(shù)資料
| 型號(hào)： | AD9991KCPZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 60/60頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CCD SIGNAL PROCESSOR 56-LFCSP |
| 產(chǎn)品變化通告： | Product Discontinuance 27/Oct/2011 |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 類型： | CCD 信號(hào)處理器，10 位 |
| 輸入類型： | 邏輯 |
| 輸出類型： | 邏輯 |
| 接口： | 3 線串口 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 56-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 56-LFCSP-VQ（8x8） |
| 包裝： | 帶卷 (TR) |
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AD9991
–9–
SYSTEM OVERVIEW
Figure 1 shows the typical system block diagram for the AD9991
used in Master mode. The CCD output is processed by the
AD9991’s AFE circuitry, which consists of a CDS, VGA, black
level clamp, and A/D converter. The digitized pixel information
is sent to the digital image processor chip, which performs the
postprocessing and compression. To operate the CCD, all CCD
timing parameters are programmed into the AD9991 from the
system microprocessor through the 3-wire serial interface. From
the system master clock, CLI, provided by the image processor
or external crystal, the AD9991 generates all of the CCD’s hori-
zontal and vertical clocks and all internal AFE clocks. External
synchronization is provided by a SYNC pulse from the micropro-
cessor, which will reset internal counters and resync the VD and
HD outputs.
Alternatively, the AD9991 may be operated in Slave mode, in
which VD and HD are provided externally from the image pro-
cessor. In this mode, all AD9991 timing will be synchronized
with VD and HD.
CCDIN
MSHUT
STROBE
H1–H4, RG, VSUB
V1–V6, VSG1–VSG5, SUBCK
CCD
V-DRIVER
AD9991
AFETG
DIGITAL
IMAGE
PROCESSING
ASIC
DOUT
DCLK
HD, VD
CLI
SERIAL
INTERFACE
SYNC
Figure 1. Typical System Block Diagram, Master Mode
The H-drivers for H1–H4 and RG are included in the AD9991,
allowing these clocks to be directly connected to the CCD.
H-drive voltage of up to 3.3 V is supported. An external V-driver
is required for the vertical transfer clocks, the sensor gate pulses,
and the substrate clock.
The AD9991 also includes programmable MSHUT and
STROBE outputs, which may be used to trigger mechanical
shutter and strobe (ash) circuitry.
Figures 2 and 3 show the maximum horizontal and vertical
counter dimensions for the AD9991. All internal horizontal and
vertical clocking is controlled by these counters to specify line
and pixel locations. Maximum HD length is 4095 pixels per line,
and maximum VD length is 4095 lines per eld.
12-BIT HORIZONTAL = 4096 PIXELS MAX
12-BIT VERTICAL = 4096 LINES MAX
MAXIMUM
FIELD
DIMENSIONS
Figure 2. Vertical and Horizontal Counters
VD
HD
MAX VD LENGTH IS 4095 LINES
CLI
MAX HD LENGTH IS 4095 PIXELS
Figure 3. Maximum VD/HD Dimensions
REV. 0
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