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| 型號： | AD9991KCPZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 3/60頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CCD SIGNAL PROCESSOR 56-LFCSP |
| 產(chǎn)品變化通告： | Product Discontinuance 27/Oct/2011 |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 類型： | CCD 信號處理器，10 位 |
| 輸入類型： | 邏輯 |
| 輸出類型： | 邏輯 |
| 接口： | 3 線串口 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 56-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 56-LFCSP-VQ（8x8） |
| 包裝： | 帶卷 (TR) |
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AD9991
–11–
12 edge locations. Table II shows the correct register values for
the corresponding edge locations.
Figure 7 shows the default timing locations for all of the high
speed clock signals.
H-Driver and RG Outputs
In addition to the programmable timing positions, the AD9991
features on-chip output drivers for the RG and H1–H4 outputs.
These drivers are powerful enough to directly drive the CCD
inputs. The H-driver and RG current can be adjusted for optimum
rise/fall time into a particular load by using the DRVCONTROL
register (Addr 0x35). The 3-bit drive setting for each output is
adjustable in 4.1 mA increments, with the minimum setting of 0
equal to OFF or three-state, and the maximum setting of 7 equal
to 30.1 mA.
As shown in Figures 5, 6, and 7, the H2 and H4 outputs are
inverses of H1 and H3, respectively. The H1/H2 crossover volt-
age is approximately 50% of the output swing. The crossover
voltage is not programmable.
Digital Data Outputs
The AD9991 data output and DCLK phases are programmable
using the DOUTPHASE register (Addr 0x37, Bits [5:0]). Any
edge from 0 to 47 may be programmed, as shown in Figure 8a.
Normally, the DOUT and DCLK signals will track in phase based
on the DOUTPHASE register contents. The DCLK output phase
can also be held xed with respect to the data outputs by chang-
ing the DCLKMODE register HIGH (Addr 0x37, Bit 6). In this
mode, the DCLK output will remain at a xed phase equal to
CLO (the inverse of CLI) while the data output phase is still
programmable.
There is a xed output delay from the DCLK rising edge to the
DOUT transition, called tOD. This delay can be programmed to
four values between 0 ns and 12 ns, by using the DOUTDELAY
register (Addr 0x037, Bits [8:7]). The default value is 8 ns.
The pipeline delay through the AD9991 is shown in Figure 8b.
After the CCD input is sampled by SHD, there is an 11-cycle
delay until the data is available.
Table I. Timing Core Register Parameters for H1, H3, RG, SHP/SHD
Parameter
Length
Range
Description
Polarity
1b
High/Low
Polarity Control for H1, H3, and RG (0 = No Inversion, 1 = Inversion)
Positive Edge
6b
0–47 Edge Location
Positive Edge Location for H1, H3, and RG
Negative Edge
6b
0–47 Edge Location
Negative Edge Location for H1, H3, and RG
Sampling Location
6b
0-47 Edge Location
Sampling Location for Internal SHP and SHD Signals
Drive Strength
3b
0–47 Current Steps
Drive Current for H1–H4 and RG Outputs (4.1 mA per Step)
H1/H3
H2/H4
RG
USING THE SAME TOGGLE POSITIONS FOR H1 AND H3 GENERATES STANDARD 2-PHASE H-CLOCKING.
CCD
SIGNAL
Figure 6. 2-Phase H-Clock Operation
Table II. Precision Timing Edge Locations
Quadrant
Edge Location (Dec)
Register Value (Dec)
Register Value (Bin)
I
0 to 11
000000 to 001011
II
12 to 23
16 to 27
010000 to 011011
III
24 to 35
32 to 43
100000 to 101011
IV
36 to 47
48 to 59
110000 to 111011
REV. 0
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