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| 型號(hào)： | AD9991KCPZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 11/60頁 |
| 文件大小： | 0K |
| 描述： | IC CCD SIGNAL PROCESSOR 56-LFCSP |
| 產(chǎn)品變化通告： | Product Discontinuance 27/Oct/2011 |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 類型： | CCD 信號(hào)處理器，10 位 |
| 輸入類型： | 邏輯 |
| 輸出類型： | 邏輯 |
| 接口： | 3 線串口 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 56-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 56-LFCSP-VQ（8x8） |
| 包裝： | 帶卷 (TR) |
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AD9991
–19–
Complete Field: Combining V-Sequences
After the V-sequences have been created, they are combined
to create different readout elds. A eld consists of up to seven
different regions, and within each region a different V-sequence
can be selected. Figure 18 shows how the sequence change
positions (SCP) designate the line boundry for each region, and
the VSEQSEL registers then select which V-sequence is used
during each region. Registers to control the VSG outputs are
also included in the Field registers.
Table VII summarizes the registers used to create the different
elds. Up to six different elds can be preprogrammed using all
of the Field registers.
The VEQSEL registers, one for each region, select which of the
10 V-sequences will be active during each region. The SWEEP
registers are used to enable SWEEP mode during any region.
The MULTI registers are used to enable Multiplier mode dur-
ing any region. The SCP registers create the line boundries for
each region. The VDLEN register species the total number of
lines in the eld. The total number of pixels per line (HDLEN) is
specied in the V-sequence registers, but the HDLAST register
species the number of pixels in the last line of the eld. The
VPATSECOND register is used to add a second V-pattern group
to the V1–6 outputs during the sensor gate (VSG) line.
The SGMASK register is used to enable or disable each indi-
vidual VSG output. There is a single bit for each VSG output:
setting the bit high will mask the output, setting it low will enable
the output. The SGPAT register assigns one of the four different
SG patterns to each VSG output. The individual SG patterns are
created separately using the SG pattern registers. The SGLINE1
register species which line in the eld will contain the VSG out-
puts. The optional SGLINE2 register allows the same VSG pulses
to be repeated on a different line.
Table VII. Field Registers
Register
Length
Range
Description
VSEQSEL
4b
0–9 V-Sequence #
Selected V-Sequence for Each Region in the Field.
SWEEP
1b
High/Low
Enables Sweep Mode for Each Region, When Set High.
MULTI
1b
High/Low
Enables Multiplier Mode for Each Region, When Set High.
SCP
12b
0–4095 Line #
Sequence Change Position for Each Region.
VDLEN
12b
0–4095 # of Lines
Total Number of Lines in Each Field.
HDLAST
12b
0–4095 # of Pixels
Length in Pixels of the Last HD Line in Each Field.
VPATSECOND
4b
0–9 V-Pattern Group #
Selected V-Pattern Group for Second Pattern Applied During VSG Line.
SGMASK
6b
High/Low, Each VSG
Set High to Mask Each Individual VSG Output. VSG1 [0], VSG2 [1],
VSG3 [2], VSG4 [3], VSG5 [4].
SGPATSEL
12b
0–3 Pattern #, Each VSG
Selects the VSG Pattern Number for Each VSG Output. VSG1 [1:0],
VSG2 [3:2], VSG3 [5:4], VSG4 [7:6], VSG5 [9:8].
SGLINE1
12b
0–4095 Line #
Selects the Line in the Field where the VSG Are Active.
SGLINE2
12b
0–4095 Line #
Selects a Second Line in the Field to Repeat the VSG Signals.
VD
REGION 0
FIELD SETTINGS:
1. SEQUENCE CHANGE POSITIONS (SCP1–6) DEFINE EACH OF THE 7 REGIONS IN THE FIELD.
2. VSEQSEL0–6 SELECTS THE DESIRED V-SEQUENCE (0–9) FOR EACH REGION.
3. SGLINE1 REGISTER SELECTS WHICH HD LINE IN THE FIELD WILL CONTAIN THE SENSOR GATE PULSE(S).
V1–V6
HD
SCP 1
SCP 2
VSEQSEL0
VSEQSEL1
SCP 3
VSEQSEL2
SCP 4
VSEQSEL3
SCP 5
VSEQSEL4
SCP 6
VSEQSEL5
VSEQSEL6
REGION 1
REGION 2
REGION 3
REGION 4
REGION 5
REGION 6
VSG
SGLINE1
Figure 18. Complete Field is Divided into Regions
REV. 0
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