參數(shù)資料
型號: AD9991KCPZRL
廠商: Analog Devices Inc
文件頁數(shù): 58/60頁
文件大小: 0K
描述: IC CCD SIGNAL PROCESSOR 56-LFCSP
產(chǎn)品變化通告: Product Discontinuance 27/Oct/2011
標準包裝: 2,500
類型: CCD 信號處理器,10 位
輸入類型: 邏輯
輸出類型: 邏輯
接口: 3 線串口
安裝類型: 表面貼裝
封裝/外殼: 56-VFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 56-LFCSP-VQ(8x8)
包裝: 帶卷 (TR)
AD9991
–7–
TERMINOLOGY
Differential Nonlinearity (DNL)
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Thus every
code must have a nite width. No missing codes guaranteed to
10-bit resolution indicates that all 1024 codes must be present
over all operating conditions.
Peak Nonlinearity
Peak nonlinearity, a full signal chain specication, refers to
the peak deviation of the output of the AD9991 from a true
straight line. The point used as zero scale occurs 0.5 LSB
before the rst code transition. Positive full scale is dened as
a level 1.5 LSB beyond the last code transition. The deviation
is measured from the middle of each particular output code to
the true straight line. The error is then expressed as a percent-
age of the 2 V ADC full-scale signal. The input signal is always
appropriately gained up to ll the ADC’s full-scale range.
Total Output Noise
The rms output noise is measured using histogram techniques.
The standard deviation of the ADC output codes is calculated in
LSB and represents the rms noise level of the total signal chain at
the specied gain setting. The output noise can be converted to
an equivalent voltage using the relationship 1 LSB = (ADC Full
Scale/2n codes), where n is the bit resolution of the ADC. For the
AD9991, 1 LSB is 1.95 mV.
Power Supply Rejection (PSR)
The PSR is measured with a step change applied to the supply
pins. The PSR specication is calculated from the change in the
data outputs for a given step change in the supply voltage.
EQUIVALENT CIRCUITS
R
AVDD
AVSS
Circuit 1. CCDIN
DVDD
DVSS
DRVSS
DRVDD
THREE-
STATE
DATA
DOUT
Circuit 2. Digital Data Outputs
DVDD
DVSS
Circuit 3. Digital Inputs
HVDD OR
RGVDD
HVSS OR
RGVSS
OUTPUT
RG, H1–H4
ENABLE
Circuit 4. H1–H4, RG Drivers
REV. 0
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