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參數(shù)資料
| 型號： | AD9991KCPZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 16/60頁 |
| 文件大小： | 0K |
| 描述： | IC CCD SIGNAL PROCESSOR 56-LFCSP |
| 產(chǎn)品變化通告： | Product Discontinuance 27/Oct/2011 |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 類型： | CCD 信號處理器，10 位 |
| 輸入類型： | 邏輯 |
| 輸出類型： | 邏輯 |
| 接口： | 3 線串口 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 56-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 56-LFCSP-VQ（8x8） |
| 包裝： | 帶卷 (TR) |
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AD9991
–23–
MODE Register
The MODE register is a single register that selects the eld tim-
ing of the AD9991. Typically, all of the eld, V-sequence, and
V-pattern group information is programmed into the AD9991
at startup. During operation, the MODE register allows the user
to select any combination of eld timing to meet the current
requirements of the system. The advantage of using the MODE
register in conjunction with preprogrammed timing is that it
greatly reduces the system programming requirements during
camera operation. Only a few register writes are required when
the camera operating mode is changed, rather than having to
write in all of the vertical timing information with each camera
mode change.
A basic still camera application might require ve different
elds of vertical timing: one for draft mode operation, one for
autofocusing, and three for still image readout. All of the reg-
ister timing information for the ve elds would be loaded at
startup. Then, during camera operation, the MODE register
would select which eld timing would be active, depending on
how the camera was being used.
Table X shows how the MODE register bits are used. The three
MSBs, D23–D21, are used to specify how many total elds will
be used. Any value from 1 to 7 can be selected using these three
bits. The remaining register bits are divided into 3-bit sections to
select which of the six elds are used and in which order. Up to
seven elds may be used in a single MODE write. The AD9991
will start with the Field timing specied by the rst Field bits,
and on the next VD will switch to the timing specied by the
second Field bits, and so on.
After completing the total number of elds specied in Bits
D23 to D21, the AD9991 will repeat by starting at the rst
Field again. This will continue until a new write to the MODE
register occurs. Figure 24 shows example MODE register set-
tings for different eld congurations.
Table X. MODE Register Data Bit Breakdown (D23 = MSB)
D23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
D0
Total Number of
7th Field
6th Field
5th Field
4th Field
3rd Field
2nd Field
1st Field
Fields to Use.
0 = Field 0
1 = 1st Field Only 5 = Field 5
5 = Field 5
7 = All 7 Fields
6, 7 = Invalid
0 = Invalid
EXAMPLE 1:
TOTAL FIELDS = 3, 1ST FIELD = FIELD 0, 2ND FIELD = FIELD 1, 3RD FIELD = FIELD 2
MODE REGISTER CONTENTS = 0x600088
FIELD 0
FIELD 1
FIELD 2
FIELD 3
FIELD 4
FIELD 5
FIELD 1
FIELD 4
FIELD 2
EXAMPLE 2:
TOTAL FIELDS = 2, 1ST FIELD = FIELD 3, 2ND FIELD = FIELD 4
MODE REGISTER CONTENTS = 0x400023
EXAMPLE 3:
TOTAL FIELDS = 4, 1ST FIELD = FIELD 5, 2ND FIELD = FIELD 1, 3RD FIELD = FIELD 4, 4TH FIELD = FIELD 2
MODE REGISTER CONTENTS = 0x80050D
Figure 24. Using the MODE Register to Select Field Timing
REV. 0
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