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參數(shù)資料
| 型號： | AD9991KCPZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 2/60頁 |
| 文件大小： | 0K |
| 描述： | IC CCD SIGNAL PROCESSOR 56-LFCSP |
| 產(chǎn)品變化通告： | Product Discontinuance 27/Oct/2011 |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 類型： | CCD 信號處理器，10 位 |
| 輸入類型： | 邏輯 |
| 輸出類型： | 邏輯 |
| 接口： | 3 線串口 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 56-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 56-LFCSP-VQ（8x8） |
| 包裝： | 帶卷 (TR) |
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AD9991
–10–
PRECISION TIMING HIGH SPEED TIMING GENERATION
The AD9991 generates high speed timing signals using the
exible Precision Timing core. This core is the foundation for
generating the timing used for both the CCD and the AFE: the
reset gate RG, horizontal drivers H1–H4, and the SHP/SHD
sample clocks. A unique architecture makes it routine for the
system designer to optimize image quality by providing precise
control over the horizontal CCD readout and the AFE correlated
double sampling.
The high speed timing of the AD9991 operates the same in either
Master or Slave mode conguration. For more information on
synchronization and pipeline delays, see the Power-Up and Syn-
chronization section.
Timing Resolution
The Precision Timing core uses a 1
master clock input (CLI)
as a reference. This clock should be the same as the CCD pixel
clock frequency. Figure 4 illustrates how the internal timing core
divides the master clock period into 48 steps or edge positions.
Using a 20 MHz CLI frequency, the edge resolution of the Preci-
sion Timing core is 1 ns. If a 1
system clock is not available, it
is also possible to use a 2
reference clock by programming the
CLIDIVIDE register (Addr 0x30). The AD9991 will then inter-
nally divide the CLI frequency by 2.
The AD9991 also includes a master clock output, CLO, which is
the inverse of CLI. This output is intended to be used as a crystal
driver. A crystal can be placed between the CLI and CLO pins to
generate the master clock for the AD9991. For more information
on using a crystal, see Figure 39.
High Speed Clock Programmability
Figure 5 shows how the high speed clocks RG, H1–H4, SHP, and
SHD are generated. The RG pulse has programmable rising and
falling edges, and may be inverted using the polarity control. The
horizontal clocks H1 and H3 have programmable rising and fall-
ing edges and polarity control. The H2 and H4 clocks are always
inverses of H1 and H3, respectively. Table I summarizes the high
speed timing registers and their parameters. Figure 6 shows the
typical 2-phase H-clock arrangement in which H3 and H4 are
programmed for the same edge location as H1 and H2.
The edge location registers are six bits wide, but there are only
48 valid edge locations available. Therefore, the register values
aremapped into four quadrants, with each quadrant containing
NOTES
PIXEL CLOCK PERIOD IS DIVIDED INTO 48 POSITIONS, PROVIDING FINE EDGE RESOLUTION FOR HIGH SPEED CLOCKS.
THERE IS A FIXED DELAY FROM THE CLI INPUT TO THE INTERNAL PIXEL PERIOD POSITIONS (
tCLIDLY = 6ns TYP).
P[0]
P[48] = P[0]
P[12]
P[24]
P[36]
1 PIXEL
PERIOD
CLI
tCLIDLY
POSITION
Figure 4. High Speed Clock Resolution from CLI Master Clock Input
H1
H2
CCD
SIGNAL
RG
PROGRAMMABLE CLOCK POSITIONS:
1. RG RISING EDGE
2. RG FALLING EDGE
3. SHP SAMPLE LOCATION
4. SHD SAMPLE LOCATION
5. H1 RISING EDGE POSITION
7. H3 RISING EDGE POSITION
H3
H4
3
4
12
56
78
6. H1 FALLING EDGE POSITION (H2 IS INVERSE OF H1)
8. H3 FALLING EDGE POSITION (H4 IS INVERSE OF H3)
Figure 5. High Speed Clock Programmable Locations
REV. 0
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