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| 型號： | AD9979BCPZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 8/56頁 |
| 文件大小： | 0K |
| 描述： | IC PROCESSOR CCD 14BIT 48-LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | CCD 信號處理器，14 位 |
| 輸入類型： | 邏輯 |
| 輸出類型： | 邏輯 |
| 接口： | 3 線串口 |
| 電流 - 電源： | 48mA |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 48-LFCSP-VQ（7x7） |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱： | AD9979BCPZRLDKR |
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AD9979
Rev. C | Page 16 of 56
HORIZONTAL CLAMPING AND BLANKING
The horizontal clamping and blanking pulses of the AD9979 are
fully programmable to suit a variety of applications. Individual
control is provided for CLPOB, PBLK, and HBLK during the
different regions of each field. This allows the dark-pixel clamping
and blanking patterns to be changed at each stage of the readout
to accommodate the different image transfer timing and high
speed line shifts.
Individual CLPOB and PBLK Patterns
The AFE horizontal timing consists of CLPOB and PBLK,
as shown in Figure 21. These two signals are independently
programmed using the registers in Table 10. The start polarity
for the CLPOB (PBLK) signal is CLPOB_POL (PBLK_POL),
and the first and second toggle positions of the pulse are
CLPOBx_TOG1 (PBLKx_TOG1) and CLPOBx_TOG2
(PBLKx_TOG2), respectively. Both signals are active low
and need to be programmed accordingly.
Two separate patterns for CLPOB and PBLK can be programmed
for each H-pattern, CLPOB0, CLPOB1, PBLK0, and PBLK1.
The CLPOB_PAT and PBLK_PAT field registers select which
of the two patterns are used in each field.
Figure 32 shows how the sequence change positions divide the
readout field into different regions. By assigning a different
H-pattern to each region, the CLPOB and PBLK signals can
change with each change in the vertical timing.
CLPOB and PBLK Masking Area
Additionally, the AD9979 allows the CLPOB and PBLK signals
to be disabled during certain lines in the field, without changing
any of the existing pattern settings. There are three sets of start
and end registers for both CLPOB and PBLK that allows the
creation of up to three masking areas for each signal.
For example, to use the CLPOB masking, program the
CLPOBMASKSTARTx and CLPOBMASKENDx registers to
specify the starting and ending lines in the field where the
CLPOB patterns are to be ignored. Figure 22 illustrates this
feature.
The masking registers are not specific to a certain H-pattern;
they are always active for any existing field of timing. To disable
the CLPOB and PBLK masking feature, set these registers to the
maximum value of 0x1FFF.
Note that to disable CLPOB and PBLK masking during
power-up, it is recommended to set CLPOBMASKSTARTx
(PBLKMASKSTARTx) to 8191 and CLPOBMASKENDx
(PBLKMASKENDx) to 0. This prevents any accidental masking
caused by different register update events.
3
2
1
HD
CLPOB
PBLK
PROGRAMMABLE SETTINGS:
1START POLARITY (CLAMP AND BLANK REGION ARE ACTIVE LOW).
2FIRST TOGGLE POSITION.
3SECOND TOGGLE POSITION.
ACTIVE
05
95
7-
02
3
Figure 21. Clamp and Preblank Pulse Placement
NO CLPOB SIGNAL
FOR LINE 600
VD
HD
NO CLPOB SIGNAL
FOR LINES 6 TO 8
CLPOBMASKSTART1 = 6
CLPOBMASKEND1 = 8
0
1
2
597
598
CLPOBMASKSTART2 = CLPOBMASKEND2 = 600
CLPOB
05
95
7-
02
4
Figure 22. CLPOB Masking Example
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