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參數(shù)資料
| 型號： | AD9979BCPZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 35/56頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PROCESSOR CCD 14BIT 48-LFCSP |
| 標準包裝： | 1 |
| 類型： | CCD 信號處理器，14 位 |
| 輸入類型： | 邏輯 |
| 輸出類型： | 邏輯 |
| 接口： | 3 線串口 |
| 電流 - 電源： | 48mA |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-VFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 48-LFCSP-VQ（7x7） |
| 包裝： | 標準包裝 |
| 其它名稱： | AD9979BCPZRLDKR |
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AD9979
Rev. C | Page 40 of 56
3-WIRE SERIAL INTERFACE TIMING
All of the internal registers of the AD9979 are accessed through a
3-wire serial interface. Each register consists of a 12-bit address
and a 28-bit data-word. Both the 12-bit address and the 28-bit
data-words are written starting with the LSB. To write to each
register, a 40-bit operation is required, as shown in Figure 56.
Although many registers are fewer than 28-bits wide, all 28 bits
must be written for each register. For example, if the register is only
20-bits wide, the upper 8 bits are don’t care bits and must be filled
with zeros during the serial write operation. If fewer than 28 data
bits are written, the register does not update with new data.
Figure 57 shows a more efficient way to write to the registers,
using the AD9979 address auto-increment capability. Using this
method, the lowest desired address is written first, followed
by multiple 28-bit data-words. Each new 28-bit data-word is
automatically written to the next highest register address. By
eliminating the need to write to each 12-bit address, faster register
loading is achieved. Continuous write operations can be used
starting with any register location.
A4
A5
A2
A3
SDATA
A0
A1
A6
A8
A9
A10
A11
D0
D1
D2
D3
D25
D26
D27
SL
A7
tLS
tDS
12-BIT ADDRESS
28-BIT DATA
5
40
6
7
8
9
10
11
12
13
14
15
16
38
39
tLH
tDH
NOTES:
1. SDATA BITS ARE LATCHED ON SCK RISING EDGES. SCK MAY IDLE HIGH OR LOW BETWEEN WRITE OPERATIONS.
2. ALL 40 BITS MUST BE WRITTEN: 12 BITS FOR ADDRESS AND 28 BITS FOR DATA.
3. IF THE REGISTER LENGTH IS <28 BITS, THEN ZEROS MUST BE USED TO COMPLETE THE 28-BIT DATA LENGTH.
4. NEW DATA VALUES ARE UPDATED IN THE SPECIFIED REGISTER LOCATION AT DIFFERENT TIMES, DEPENDING ON THE
PARTICULAR REGISTER WRITTEN TO. SEE THE UPDATING OF NEW REGISTER VALUES SECTION FOR MORE INFORMATION.
SCK
12
34
05
95
7-
0
58
Figure 56. Serial Write Operation
SDATA
A0
A1
A2
A10
A11
D0
D1
D26
D27
SCK
SL
A3
NOTES:
1. MULTIPLE SEQUENTIAL REGISTERS MAY BE LOADED CONTINUOUSLY.
2. THE FIRST (LOWEST ADDRESS) REGISTER ADDRESS IS WRITTEN, FOLLOWED BY MULTIPLE 28-BIT DATA-WORDS.
3. THE ADDRESS AUTOMATICALLY INCREMENTS WITH EACH 28-BIT DATA-WORD (ALL 28 BITS MUST BE WRITTEN).
4. SL IS HELD LOW UNTIL THE LAST DESIRED REGISTER HAS BEEN LOADED.
D0
D1
D26
D27
D0
DATA FOR STARTING
REGISTER ADDRESS
DATA FOR NEXT
REGISTER ADDRESS
D2
D1
1
40
2
3
4
111213
14
39
42
41
68
67
70
69
71
05
95
7-
0
59
Figure 57. Continuous Serial Write Operation
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