參數(shù)資料
型號(hào)： AD9979BCPZRL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 19/56頁(yè)
文件大?。?/td> 0K
描述： IC PROCESSOR CCD 14BIT 48-LFCSP
標(biāo)準(zhǔn)包裝： 1
類型： CCD 信號(hào)處理器，14 位
輸入類型： 邏輯
輸出類型： 邏輯
接口： 3 線串口
電流 - 電源： 48mA
安裝類型： 表面貼裝
封裝/外殼： 48-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 48-LFCSP-VQ（7x7）
包裝： 標(biāo)準(zhǔn)包裝
其它名稱： AD9979BCPZRLDKR
AD9979
Rev. C | Page 26 of 56
HORIZONTAL TIMING SEQUENCE EXAMPLE
Figure 34 shows an example of a CCD layout. The horizontal
register contains 28 dummy pixels, which occur on each line
clocked from the CCD. In the vertical direction, there are 10 optical
black (OB) lines at the front of the readout and 2 OB lines at the
back of the readout. The horizontal direction has 4 OB pixels in
the front and 48 in the back.
Figure 35 shows the basic sequence layout to use during the
effective pixel readout. The 48 OB pixels at the end of each line
are used for the CLPOB signals. PBLK is optional and is often
used to blank the digital outputs during the HBLK time. HBLK
is used during the vertical shift interval.
Because PBLK is used to isolate the CDS input (see the Analog
Front-End Description and Operation section), the PBLK signal
cannot be used during CLPOB operation. The change in the
offset behavior that occurs during PBLK impacts the accuracy
of the CLPOB circuitry.
The HBLK, CLPOB, and PBLK parameters are programmed in
the V-sequence registers. More elaborate clamping schemes can
be used, such as adding in a separate sequence to clamp in the
entire shield OB lines. This requires configuring a separate
V-sequence for clocking out the OB lines.
The CLPOB mask registers are also useful for disabling the
CLPOB on a few lines without affecting the setup of the
clamping sequences. It is important to use CLPOB only during
valid OB pixels. During other portions on the frame timing, such
as during vertical blanking or SG line timing, the CCD does not
output valid OB pixels. Any CLPOB pulses that occur during this
time cause errors in clamping operation, and therefore, cause
changes in the black level of the image.
HORIZONTAL CCD REGISTER
EFFECTIVE IMAGE AREA
28 DUMMY PIXELS
48 OB PIXELS
4 OB PIXELS
10 VERTICAL
OB LINES
2 VERTICAL
OB LINES
V
H
05
95
7-
0
36
Figure 34. Example CCD Configuration
VERTICAL SHIFT
VERT. SHIFT
CCD OUTPUT
SHP
SHD
H1/H3
H2/H4
HBLK
PBLK
CLPOB
OB
DUMMY
EFFECTIVE PIXELS
OB
HD
NOTES
1. IT IS RECOMMENDED THAT PBLK ACTIVE (LOW) NOT BE USED DURING CLPOB ACTIVE (LOW).
0
59
57
-0
37
Figure 35. Horizontal Sequence Example
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