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| 型號： | AD9979BCPZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 25/56頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PROCESSOR CCD 14BIT 48-LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | CCD 信號處理器，14 位 |
| 輸入類型： | 邏輯 |
| 輸出類型： | 邏輯 |
| 接口： | 3 線串口 |
| 電流 - 電源： | 48mA |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 48-LFCSP-VQ（7x7） |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱： | AD9979BCPZRLDKR |
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AD9979
Rev. C | Page 31 of 56
ANALOG FRONT-END DESCRIPTION AND OPERATION
6dB TO 42dB
CCDINP
CLI
DIGITAL
FILTER
CLPOB
DC RESTORE
OPTICAL BLACK
CLAMP
14-BIT
ADC
VGA
DAC
CDS
INTERNAL
VREF
2V FULL SCALE
SHP
SHD
1.2V
OUTPUT
DATA
LATCH
REFT
REFB
DOUT PHASE
DOUT
V-H
TIMING
GENERATION
SHP SHD
DOUT
PHASE
CLPOB
PBLK
0.4V
1.4V
AD9979
0.1F
VGA GAIN
REGISTER
0.1F 0.1F
CLAMP-LEVEL
REGISTER
14
PBLK
–3dB, 0dB,
+3dB, +6dB
PBLK
PBLK (WHEN DCBYP = 1)
SHP
S11
S22
BLANK TO
ZERO OR
CLAMP LEVEL
1S1 IS NORMALLY CLOSED.
2S2 IS NORMALLY OPEN.
D0 TO D13
CDS GAIN
REGISTER
VD
HD
PRECISION
TIMING
GENERATION
0
59
57
-0
44
Figure 42. Analog Front End Functional Block Diagram
The AD9979 signal processing chain is shown in Figure 42.
Each processing step is essential in achieving a high quality
image from the raw CCD pixel data.
DC Restore
To reduce the large dc offset of the CCD output signal, a dc
restore circuit is used with an external 0.1 μF series coupling
capacitor. This restores the dc level of the CCD signal to
approximately 1.2 V, to be compatible with the 1.8 V core
supply voltage of the AD9979. The dc restore switch is active
during the SHP sample pulse time.
The dc restore circuit can be disabled when the optional PBLK
signal is used to isolate large signal swings from the CCD input
(see the Analog Preblanking section). Bit 6 of Address 0x00
controls whether the dc restore is active during the PBLK interval
(see Table 24).
Analog Preblanking
During certain CCD blanking or substrate clocking intervals,
the CCD input signal to the AD9979 can increase in amplitude
beyond the recommended input range. The PBLK signal can
be used to isolate the CDS input from large signal swings. As
shown in Figure 42, when PBLK is active (low), the CDS input
is isolated from the CCDINx pin (S1 open) and is internally
shorted to ground (S2 closed).
During the PBLK active time, the ADC outputs can be pro-
grammed to output all zeros or the programmed clamp level.
Note that because the CDS input is shorted during PBLK, the
CLPOB pulse must not be used during the same active time as
the PBLK pulse.
Correlated Double Sampler (CDS)
The CDS circuit samples each CCD pixel twice to extract the
video information and to reject low frequency noise. The
timing shown in Figure 19 illustrates how the two internally
generated CDS clocks, SHP and SHD, are used to sample the
reference level and to sample the CCD signal level, respectively.
The placement of the SHP and SHD sampling edges is deter-
mined by the setting of the SHPLOC and SHDLOC registers,
located at Address 0x36. Placement of these two clock signals is
critical in achieving the best performance from the CCD.
The CDS gain is variable in four steps, set by using CDSGAIN
(Address 0x04): 3 dB, 0 dB (default), +3 dB, and +6 dB (see
Table 24). Improved noise performance results from using the
+3 dB and +6 dB settings, but the input range is reduced with
these settings (see Table 4).
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