參數(shù)資料
型號(hào): AD9979BCPZRL
廠商: Analog Devices Inc
文件頁(yè)數(shù): 21/56頁(yè)
文件大小: 0K
描述: IC PROCESSOR CCD 14BIT 48-LFCSP
標(biāo)準(zhǔn)包裝: 1
類型: CCD 信號(hào)處理器,14 位
輸入類型: 邏輯
輸出類型: 邏輯
接口: 3 線串口
電流 - 電源: 48mA
安裝類型: 表面貼裝
封裝/外殼: 48-VFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 48-LFCSP-VQ(7x7)
包裝: 標(biāo)準(zhǔn)包裝
其它名稱: AD9979BCPZRLDKR
AD9979
Rev. C | Page 28 of 56
Table 16. GPO Registers (Address 0x52 to Address 0x59)
Name
Length
Range
Description
GP1_PROTOCOL
2 bits
0 to 3
0x0 = idle.
GP2_PROTOCOL
2 bits
0 to 3
0x1 = manual, no counter association.
0x2 = link to primary counter.
0x3 = primary repeat. Allows GP signals to repeat with RapidShot.
GP_LINE_MODE
2 bits
Off/on
Enables general-purpose output signals on every line.
0 = disable.
1 = enable.
2 bits
Low/high
Starting polarity for general-purpose signals. Only updated during PROTOCOL = 1.
GPO_OUTPUT_EN
2 bits
Off/on
0 = disable GPOx. Output pins are in high-Z state (default).
1 = enable GPO1 to GPO2 outputs (1 bit per output).
SEL_GPOx1
2 bits
0 to 3
Select signal for GPO output.
0 = use GP toggles.
1 = use CLPOB.
2 = use PBLK.
3 = use high speed timing signal.
2 bits
0 to 3
Select GPO output high speed timing signal used.
0 = use delayed CLI.
1 = use delayed ADC output latch clock.
2 = use delayed SHD sample clock.
3 = use delayed SHP sample clock.
HBLK_EXT
1 bit
Off/on
1 = enable external HBLK signal to be input to GPO2 pin.
GP_LUT_EN
2 bits
0 = disabled.
GP12_LUT
4 bits
Logic setting
Desired logic to be realized on GPO1 combined with GPO2. Example logic settings
for GP12_LUT:
0x6 = GPO1 XOR GPO2 (See Figure 41).
0x7 = GPO1 NAND GPO2.
0x8 = GPO1 AND GPO2.
0xE = GPO1 OR GPO2.
GPTx_TOGy_FIELD1, 2
4 bits
0 to 15
Field of activity, relative to primary counter for toggle.
GPTx_TOGy_LINE1, 2
13 bits
0 to 8191
Line of activity for toggle.
13 bits
0 to 8191
Pixel of activity for toggle.
1 The variable x represents the general-purpose output, 1 or 2.
2 The variable y represents the toggle, 1 or 2.
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