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參數(shù)資料
| 型號： | AD9959/PCBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 44/44頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION FOR AD9959 |
| 產(chǎn)品培訓(xùn)模塊： | Direct Digital Synthesis Tutorial Series (1 of 7): Introduction Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator |
| 設(shè)計資源： | Phase Coherent FSK Modulator (CN0186) AD9958/59 Eval Brd Schematics AD9958/59 Eval Brd Gerber Files AD9959 Eval Brd BOM |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 計時，直接數(shù)字合成（DDS） |
| 嵌入式： | 否 |
| 已用 IC / 零件： | AD9959 |
| 主要屬性： | 10 位數(shù)模轉(zhuǎn)換器，32 位調(diào)節(jié)字寬 |
| 次要屬性： | 4 通道 |
| 已供物品： | 板，線纜，軟件 |
| 其它名稱： | AD9959/PCB AD9959/PCB-ND Q2548077 |
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AD9959
Rev. B | Page 9 of 44
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
NC = NO CONNECT
1
SYNC_IN
2
SYNC_OUT
3
MASTER_RESET
4
PWR_DWN_CTL
5
AVDD
6
AGND
7
AVDD
8
CH2_IOUT
9
CH2_IOUT
10
AGND
11
AVDD
12
AGND
13
CH3_IOUT
14
CH3_IOUT
35
CH1_IOUT
36
CH1_IOUT
37
AVDD
38
AGND
39
AVDD
40
P0
41
P1
42
P2
34
AGND
33
AVDD
32
AGND
31
AVDD
30
CH0_IOUT
29
CH0_IOUT
15
A
V
D
16
A
G
N
D
17
D
A
C
_R
S
E
T
19
A
V
D
21
A
V
D
20
A
G
N
D
22
R
E
F
_C
L
K
23
R
E
F
_C
L
K
24
C
L
K
_M
O
D
E
_S
E
L
25
A
G
N
D
26
A
V
D
27
L
O
P
_F
IL
T
E
R
28
A
G
N
D
18
A
G
N
D
45
D
V
D
46
I/
O
_U
P
D
A
T
E
47
C
S
48
S
C
L
K
49
D
V
D
_I
/O
50
S
D
IO
_0
51
S
D
IO
_1
52
S
D
IO
_2
53
S
D
IO
_3
54
S
Y
N
C
_C
L
K
44
D
G
N
D
43
P
3
TOP VIEW
(Not to Scale)
AD9959
55
D
V
D
56
D
G
N
D
05
24
6-
0
03
NOTES
1. THE EXPOSED EPAD ON BOTTOM SIDE OF PACKAGE IS
AN ELECTRICAL CONNECTION AND MUST BE
SOLDERED TO GROUND.
2. PIN 49 IS DVDD_I/O AND IS TIED TO 3.3V.
Figure 3. Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
SYNC_IN
I
Used to Synchronize Multiple AD9959 Devices. Connects to the SYNC_OUT pin of
the master AD9959 device.
2
SYNC_OUT
O
Used to Synchronize Multiple AD9959 Devices. Connects to the SYNC_IN pin of the
slave AD9959 devices.
3
MASTER_RESET
I
Active High Reset Pin. Asserting the MASTER_RESET pin forces the AD9959 internal
registers to their default state, as described in the Register Maps and Bit Descriptions
section.
4
PWR_DWN_CTL
I
External Power-Down Control.
5, 7, 11, 15, 19, 21,
26, 31, 33, 37, 39
AVDD
I
Analog Power Supply Pins (1.8 V).
6, 10, 12, 16, 18, 20,
25, 28, 32, 34, 38
AGND
I
Analog Ground Pins.
45, 55
DVDD
I
Digital Power Supply Pins (1.8 V).
44, 56
DGND
I
Digital Power Ground Pins.
8
CH2_IOUT
O
True DAC Output. Terminates into AVDD.
9
CH2_IOUT
O
Complementary DAC Output. Terminates into AVDD.
13
CH3_IOUT
O
True DAC Output. Terminates into AVDD.
14
CH3_IOUT
O
Complementary DAC Output. Terminates into AVDD.
17
DAC_RSET
I
Establishes the Reference Current for All DACs. A 1.91 kΩ resistor (nominal) is
connected from Pin 17 to AGND.
22
REF_CLK
I
Complementary Reference Clock/Oscillator Input. When the REF_CLK is operated
in single-ended mode, this pin should be decoupled to AVDD or AGND with a
0.1 μF capacitor.
23
REF_CLK
I
Reference Clock/Oscillator Input. When the REF_CLK is operated in single-ended
mode, this is the input. See the Modes of Operation section for the reference clock
configuration.
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