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參數(shù)資料
| 型號(hào)： | AD9959/PCBZ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 36/44頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION FOR AD9959 |
| 產(chǎn)品培訓(xùn)模塊： | Direct Digital Synthesis Tutorial Series (1 of 7): Introduction Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator |
| 設(shè)計(jì)資源： | Phase Coherent FSK Modulator (CN0186) AD9958/59 Eval Brd Schematics AD9958/59 Eval Brd Gerber Files AD9959 Eval Brd BOM |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 計(jì)時(shí)，直接數(shù)字合成（DDS） |
| 嵌入式： | 否 |
| 已用 IC / 零件： | AD9959 |
| 主要屬性： | 10 位數(shù)模轉(zhuǎn)換器，32 位調(diào)節(jié)字寬 |
| 次要屬性： | 4 通道 |
| 已供物品： | 板，線纜，軟件 |
| 其它名稱： | AD9959/PCB AD9959/PCB-ND Q2548077 |
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AD9959
Rev. B | Page 41 of 44
DESCRIPTIONS FOR CHANNEL REGISTERS
Channel Function Register (CFR)—Address 0x03
Three bytes are assigned to this register.
Table 34. Bit Descriptions for CFR
Bit
Mnemonic
Description
23:22
Amplitude frequency
phase (AFP) select
Controls what type of modulation is to be performed for that channel. See the Modulation Mode section
for details.
21:16
Open
15
Linear sweep no-dwell
0 = the linear sweep no-dwell function is inactive (default).
1 = the linear sweep no-dwell function is active. If CFR[15] is active, the linear sweep no-dwell function is
activated. See the Linear Sweep Mode section for details. If CFR[14] is clear, this bit is don’t care.
14
Linear sweep enable
0 = the linear sweep capability is inactive (default).
1 = the linear sweep capability is enabled. When enabled, the delta frequency tuning word is applied to
the frequency accumulator at the programmed ramp rate.
13
Load SRR at
I/O_UPDATE
0 = the linear sweep ramp rate timer is loaded only upon timeout (timer = 1) and is not loaded because
of an I/O_UPDATE input signal (default).
1 = the linear sweep ramp rate timer is loaded upon timeout (timer = 1) or at the time of an I/O_UPDATE
input signal.
12:11
Open
10
Must be 0
Must be set to 0.
9:8
DAC full-scale current
control
11 = the DAC is at the largest LSB value (default).
See Table 5 for other settings.
7
Digital power-down
0 = the digital core is enabled for operation (default).
1 = the digital core is disabled and is in its lowest power dissipation state.
6
DAC power-down
0 = the DAC is enabled for operation (default).
1 = the DAC is disabled and is in its lowest power dissipation state.
5
Matched pipe delays
0 = matched pipe delay mode is inactive (default).
active
1 = matched pipe delay mode is active. See the Single-Tone Mode—Matched Pipeline Delay section for
details.
4
Autoclear sweep
accumulator
0 =
the current state of the sweep accumulator is not impacted by receipt of an I/O_UPDATE signal
(default).
1 = t
he sweep accumulator is automatically and synchronously cleared for one cycle upon receipt
of an I/O_UPDATE signal.
3
Clear sweep
0 = the sweep accumulator functions as normal (default).
accumulator
1 = the sweep accumulator memory elements are asynchronously cleared.
2
Autoclear phase
accumulator
0 = t
he current state of the phase accumulator is not impacted by receipt of an I/O_UPDATE signal
(default).
1 = t
he phase accumulator is automatically and synchronously cleared for one cycle upon receipt
of an I/O_UPDATE signal.
1
Clear phase
0 = the phase accumulator functions as normal (default).
accumulator
1 = the phase accumulator memory elements are asynchronously cleared.
0
Sine wave output
0 = the angle-to-amplitude conversion logic employs a cosine function (default).
enable
1 = the angle-to-amplitude conversion logic employs a sine function.
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