參數(shù)資料
型號: AD9959/PCBZ
廠商: Analog Devices Inc
文件頁數(shù): 37/44頁
文件大?。?/td> 0K
描述: BOARD EVALUATION FOR AD9959
產(chǎn)品培訓(xùn)模塊: Direct Digital Synthesis Tutorial Series (1 of 7): Introduction
Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action
Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter
Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction
Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter
Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator
設(shè)計資源: Phase Coherent FSK Modulator (CN0186)
AD9958/59 Eval Brd Schematics
AD9958/59 Eval Brd Gerber Files
AD9959 Eval Brd BOM
標(biāo)準(zhǔn)包裝: 1
主要目的: 計時,直接數(shù)字合成(DDS)
嵌入式:
已用 IC / 零件: AD9959
主要屬性: 10 位數(shù)模轉(zhuǎn)換器,32 位調(diào)節(jié)字寬
次要屬性: 4 通道
已供物品: 板,線纜,軟件
其它名稱: AD9959/PCB
AD9959/PCB-ND
Q2548077
AD9959
Rev. B | Page 42 of 44
Channel Frequency Tuning Word 0 (CFTW0)—Address 0x04
Four bytes are assigned to this register.
Table 35. Description for CFTW0
Bit
Mnemonic
Description
31:0
Frequency Tuning Word 0
Frequency Tuning Word 0 for each channel.
Channel Phase Offset Word 0 (CPOW0)—Address 0x05
Two bytes are assigned to this register.
Table 36. Description for CPOW0
Bit
Mnemonic
Description
15:14
Open
13:0
Phase Offset Word 0
Phase Offset Word 0 for each channel
Amplitude Control Register (ACR)—Address0x06
Three bytes are assigned to this register.
Table 37. Description for ACR
Bit
Mnemonic
Description
23:16
Amplitude ramp rate
Amplitude ramp rate value.
15:14
Increment/decrement
step size
Amplitude increment/decrement step size.
13
Open
12
Amplitude multiplier
enable
0 = amplitude multiplier is disabled. The clocks to this scaling function (auto RU/RD) are stopped
for power saving, and the data from the DDS core is routed around the multipliers (default).
1 = amplitude multiplier is enabled.
11
Ramp-up/ramp-down
This bit is valid only when ACR[12] is active high.
enable
0 = when ACR[12] is active, Logic 0 on ACR[11] enables the manual RU/RD operation. See the
Output Amplitude Control Mode section for details (default).
1 = if ACR[12] is active, a Logic 1 on ACR[11] enables the auto RU/RD operation. See the Output
Amplitude Control Mode section for details.
10
Load ARR at
I/O_UPDATE
0 = the amplitude ramp rate timer is loaded only upon timeout (timer = 1) and is not loaded due
to an I/O_UPDATE input signal (default).
1 = the amplitude ramp rate timer is loaded upon timeout (timer = 1) or at the time of an
I/O_UPDATE input signal.
9:0
Amplitude scale factor
Amplitude scale factor for each channel.
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