參數(shù)資料
型號(hào)： AD9959/PCBZ
廠商： Analog Devices Inc
文件頁數(shù)： 35/44頁
文件大?。?/td> 0K
描述： BOARD EVALUATION FOR AD9959
產(chǎn)品培訓(xùn)模塊： Direct Digital Synthesis Tutorial Series (1 of 7): Introduction
Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action
Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter
Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction
Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter
Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator
設(shè)計(jì)資源： Phase Coherent FSK Modulator (CN0186)
AD9958/59 Eval Brd Schematics
AD9958/59 Eval Brd Gerber Files
AD9959 Eval Brd BOM
標(biāo)準(zhǔn)包裝： 1
主要目的： 計(jì)時(shí)，直接數(shù)字合成（DDS）
嵌入式： 否
已用 IC / 零件： AD9959
主要屬性： 10 位數(shù)模轉(zhuǎn)換器，32 位調(diào)節(jié)字寬
次要屬性： 4 通道
已供物品： 板，線纜，軟件
其它名稱： AD9959/PCB
AD9959/PCB-ND
Q2548077
AD9959
Rev. B | Page 40 of 44
Bit
Mnemonic
Description
5
SYNC_CLK disable
0 = the SYNC_CLK pin is active (default).
1 = the SYNC_CLK pin assumes a static Logic 0 state (disabled). In this state, the pin drive logic is
shut down. However, the synchronization circuitry remains active internally to maintain normal
device operation.
4
DAC reference power-down
0 = DAC reference is enabled (default).
1 = DAC reference is powered down.
3:2
Open
See the Synchronizing Multiple AD9959 Devices section for details.
1
Manual hardware sync
0 = the manual hardware synchronization feature of multiple devices is inactive (default).
1 = the manual hardware synchronization feature of multiple devices is active.
0
Manual software sync
0 = the manual software synchronization feature of multiple devices is inactive (default).
1 = the manual software synchronization feature of multiple devices is active. See the
Function Register 2 (FR2)—Address 0x02
Two bytes are assigned to this register. The FR2 is used to control the various functions, features, and modes of the AD9959.
Table 33. Bit Descriptions for FR2
Bit
Mnemonic
Description
15
All channels autoclear sweep
accumulator
0 = a new delta word is applied to the input, as in normal operation, but not loaded into the
accumulator (default).
1 = this bit automatically and synchronously clears (loads 0s into) the sweep accumulator for one
cycle upon reception of the I/O_UPDATE sequence indicator on all four channels.
14
All channels clear
0 = the sweep accumulator functions as normal (default).
sweep accumulator
1 = the sweep accumulator memory elements for all four channels are asynchronously cleared.
13
All channels autoclear phase
accumulator
0 = a new frequency tuning word is applied to the inputs of the phase accumulator, but not
loaded into the accumulator (default).
1 = this bit automatically and synchronously clears (loads 0s into) the phase accumulator for one
cycle upon receipt of the I/O update sequence indicator on all four channels.
12
All channels clear phase
0 = the phase accumulator functions as normal (default).
accumulator
1 = the phase accumulator memory elements for all four channels are asynchronously cleared.
11:8
Open
7
Auto sync enable
See the Synchronizing Multiple AD9959 Devices section for more details.
6
Multidevice sync master enable
See the Synchronizing Multiple AD9959 Devices section for more details.
5
Multidevice sync status
See the Synchronizing Multiple AD9959 Devices section for more details.
4
Multidevice sync mask
See the Synchronizing Multiple AD9959 Devices section for more details.
3: 2
Open
1:0
System clock offset
See the Synchronizing Multiple AD9959 Devices section for more details.
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