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參數(shù)資料
| 型號(hào)： | AD9959/PCBZ |
| 廠(chǎng)商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 19/44頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION FOR AD9959 |
| 產(chǎn)品培訓(xùn)模塊： | Direct Digital Synthesis Tutorial Series (1 of 7): Introduction Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator |
| 設(shè)計(jì)資源： | Phase Coherent FSK Modulator (CN0186) AD9958/59 Eval Brd Schematics AD9958/59 Eval Brd Gerber Files AD9959 Eval Brd BOM |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 計(jì)時(shí)，直接數(shù)字合成（DDS） |
| 嵌入式： | 否 |
| 已用 IC / 零件： | AD9959 |
| 主要屬性： | 10 位數(shù)模轉(zhuǎn)換器，32 位調(diào)節(jié)字寬 |
| 次要屬性： | 4 通道 |
| 已供物品： | 板，線(xiàn)纜，軟件 |
| 其它名稱(chēng)： | AD9959/PCB AD9959/PCB-ND Q2548077 |
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AD9959
Rev. B | Page 26 of 44
This load and countdown operation continues for as long as the
timer is enabled. However, the count can be reloaded before
reaching 1 by either of the following two methods:
Method 1 is to change the profile pin. When the profile pin
changes from Logic 0 to Logic 1, the rising sweep ramp rate
(RSRR) register value is loaded into the ramp rate timer,
which then proceeds to count down as normal. When the
profile pin changes from Logic 1 to Logic 0, the falling sweep
ramp rate (FSRR) register value is loaded into the ramp
rate timer, which then proceeds to count down as normal.
Method 2 is to set the CFR[14] bit and issue an I/O update.
If sweep is enabled and CFR[14] is set, the ramp rate timer
loads the value determined by the profile pin. If the profile
pin is high, the ramp rate timer loads the RSRR; if the profile
pin is low, the ramp rate timer loads FSRR.
Frequency Linear Sweep Example: AFP Bits = 10
In the following example, the modulation level bits (FR1[9:8]) = 00,
the linear sweep enable bit (CFR[14]) = 1, and the linear sweep
no-dwell bit (CFR[15]) = 0.
In linear sweep mode, when the profile pin transitions from low
to high, the RDW is applied to the input of the sweep accumulator
and the RSRR register is loaded into the sweep rate timer.
The RDW accumulates at the rate given by the rising sweep
ramp rate (RSRR) bits until the output is equal to the CW1
register value. The sweep is then complete, and the output is
held constant in frequency.
When the profile pin transitions from high to low, the FDW is
applied to the input of the sweep accumulator and the FSRR bits
are loaded into the sweep rate timer.
The FDW accumulates at the rate given by the falling sweep ramp
rate (FSRR) until the output is equal to the CFTW0 register
(Register 0x04) value. The sweep is then complete, and the output
is held constant in frequency.
depicts a frequency sweep with no-dwell mode disabled. In this
mode, the output follows the state of the profile pin. A phase or
amplitude sweep works in the same manner.
LINEAR SWEEP NO-DWELL MODE
If the linear sweep no-dwell bit is set (CFR[15]), the rising sweep is
started in an identical manner to the dwell linear sweep mode;
that is, upon detecting Logic 1 on the profile input pin, the rising
sweep action is initiated. The word continues to sweep up at the
rate set by the rising sweep ramp rate at the resolution set by the
rising delta word until it reaches the terminal value. Upon reaching
the terminal value, the output immediately reverts to the starting
point and remains until Logic 1 is detected on the profile pin.
Figure 38 shows an example of the no-dwell mode. The points
labeled A indicate where a rising edge is detected on the profile
pin, and the points labeled B indicate where the AD9959 has
determined that the output has reached E0 and reverts to S0.
The falling sweep ramp rate bits (LSRR[15:8]) and the falling
delta word bits (FDW[31:0]) are unused in this mode.
RATE TIME
LOAD CONTROL
LOGIC
LIMIT LOGIC TO
KEEP SWEEP BETWEEN
S0 AND E0
RAMP RATE TIMER:
8-BIT LOADABLE DOWN COUNTER
ACCUMULATOR RESET
LOGIC
0
1
MUX
0
1
MUX
0
1
MUX
PROFILE PIN
0
1
8
MUX
0
1
MUX
FDW
RDW
FSRR
RSRR
0
32
PROFILE PIN
Z–1
CW1
05
24
6-
0
21
SWEEP ACCUMULATOR
SWEEP ADDER
CFTW0
Figure 37. Linear Sweep Block Diagram
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