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參數(shù)資料
| 型號： | AD9959/PCBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 25/44頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR AD9959 |
| 產(chǎn)品培訓(xùn)模塊： | Direct Digital Synthesis Tutorial Series (1 of 7): Introduction Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator |
| 設(shè)計資源： | Phase Coherent FSK Modulator (CN0186) AD9958/59 Eval Brd Schematics AD9958/59 Eval Brd Gerber Files AD9959 Eval Brd BOM |
| 標準包裝： | 1 |
| 主要目的： | 計時，直接數(shù)字合成（DDS） |
| 嵌入式： | 否 |
| 已用 IC / 零件： | AD9959 |
| 主要屬性： | 10 位數(shù)模轉(zhuǎn)換器，32 位調(diào)節(jié)字寬 |
| 次要屬性： | 4 通道 |
| 已供物品： | 板，線纜，軟件 |
| 其它名稱： | AD9959/PCB AD9959/PCB-ND Q2548077 |
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AD9959
Rev. B | Page 31 of 44
SERIAL I/O PORT
OVERVIEW
The AD9959 serial I/O port offers multiple configurations to
provide significant flexibility. The serial I/O port offers an SPI-
compatible mode of operation that is virtually identical to the
SPI operation found in earlier Analog Devices DDS products.
The flexibility is provided by four data pins (SDIO_0, SDIO_1,
SDIO_2, SDIO_3) that allow four programmable modes of
serial I/O operation.
Three of the four data pins (SDIO_1, SDIO_2, SDIO_3) can be
used for functions other than serial I/O port operation. These pins
can also be used to initiate a ramp-up or ramp-down (RU/RD)
of the 10-bit amplitude output scalar. In addition, SDIO_3 can
be used to provide the SYNC_I/O function that resynchronizes
the serial I/O port controller if it is out of proper sequence.
The maximum speed of the serial I/O port SCLK is 200 MHz,
but the four data pins (SDIO_0, SDIO_1, SDIO_2, SDIO_3)
can be used to further increase data throughput. The maximum
data throughput using all the SDIO pins (SDIO_0, SDIO_1,
SDIO_2, SDIO_3) is 800 Mbps.
Note that all channels share Register 0x03 to Register 0x18, which
are shown in the Register Maps and Bit Descriptions section.
This address sharing enables all four DDS channels to be written
to simultaneously. For example, if a common frequency tuning
word is desired for all four channels, it can be written once
through the serial I/O port to all four channels. This is the
default mode of operation (all channels enabled). To enable
each channel to be independent, the four channel enable bits
found in the channel select register (CSR, Register 0x00) must
be used.
There are effectively four sets or copies of addresses (Register 0x03
to Register 0x18) that the channel enable bits can access to provide
channel independence. See the Descriptions for Control Registers
section for further details of programming channels that are
common to or independent from each other. To properly read
back Register 0x03 to Register 0x18, the user must enable only
one channel enable bit at a time.
Serial operation of the AD9959 occurs at the register level,
not the byte level; that is, the controller expects that all bytes
contained in the register address are accessed. The SYNC_I/O
function can be used to abort an I/O operation, thereby allowing
fewer than all bytes to be accessed. This feature can be used to
program only a part of the addressed register. Note that only
completed bytes are affected.
There are two phases to a serial communications cycle. Phase 1
is the instruction cycle, which writes the instruction byte into
the AD9959. Each bit of the instruction byte is registered on
each corresponding rising edge of SCLK. The instruction byte
defines whether the upcoming data transfer is a write or read
operation. The instruction byte contains the serial address of
the address register.
Phase 2 of the I/O cycle consists of the actual data transfer
(write/read) between the serial port controller and the serial
port buffer. The number of bytes transferred during this phase
of the communication cycle is a function of the register being
accessed. The actual number of additional SCLK rising edges
required for the data transfer and instruction byte depends on
the number of bytes in the register and the serial I/O mode of
operation.
For example, when accessing Function Register 1 (FR1), which
is three bytes wide, Phase 2 of the I/O cycle requires that three
bytes be transferred. After transferring all data bytes per the
instruction byte, the communication cycle is completed for that
register.
At the completion of a communication cycle, the AD9959 serial
port controller expects the next set of rising SCLK edges to be
the instruction byte for the next communication cycle. All data
written to the AD9959 is registered on the rising edge of SCLK.
Data is read on the falling edge of SCLK (see Figure 43 through
are described in Table 25.
tPRE
tDSU
tSCLK
tSCLKPWL
tSCLKPWH
tDHLD
CS
SCLK
SDIO_x
05
24
6-
02
3
Figure 41. Setup and Hold Timing for the Serial I/O Port
tDV
CS
SCLK
SDIO_x
SDO (SDIO_2)
05
24
6-
0
24
Figure 42. Timing Diagram for Data Read for Serial I/O Port
Table 25. Timing Specifications
Parameter
Min
Unit
Description
tPRE
1.0
ns min
CS setup time
tSCLK
5.0
ns min
Period of serial data clock
tDSU
2.2
ns min
Serial data setup time
tSCLKPWH
2.2
ns min
Serial data clock pulse width high
tSCLKPWL
1.6
ns min
Serial data clock pulse width low
tDHLD
0
ns min
Serial data hold time
tDV
12
ns min
Data valid time
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