參數(shù)資料
型號(hào)： AD9942BBCZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 36/36頁(yè)
文件大?。?/td> 0K
描述： IC PROCESSOR SGNL 14B 100CSPBGA
標(biāo)準(zhǔn)包裝： 1
類型： CCD 信號(hào)處理器，14 位
應(yīng)用： 數(shù)碼相機(jī)
安裝類型： 表面貼裝
封裝/外殼： 100-LFBGA，CSPBGA
供應(yīng)商設(shè)備封裝： 100-CSBGA（9x9）
包裝： 托盤
AD9942
Rev. A | Page 9 of 36
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
05
240
-00
2
1
A1 CORNER
INDEX AREA
23456789 10
A
B
C
D
E
F
G
H
J
K
AD9942
TOP VIEW
(Not to Scale)
Figure 2. Pin Configuration
Table 7. Pin Function Descriptions
Ball Location
Mnemonic
Type1
Description
B2
SL_A
DI
6-Wire Serial Load for Channel A
C2
SDATA_A
DI
6-Wire Serial Data for Channel A
D2
SCK_A
DI
6-Wire Serial Clock for Channel A
C1
REFT_A
AO
Reference Top Decoupling for Channel A (decouple with 1.0 μF to AVSS_A)
D1
REFB_A
AO
Reference Bottom Decoupling for Channel A (decouple with 1.0 μF to AVSS_A)
A1
CCDIN_A
AI
Analog Input for Channel A CCD Signal (connect through series 0.1 μF capacitor)
F4
H1A
DO
CCD Horizontal Clock 1 for Channel A
F3
H2A
DO
CCD Horizontal Clock 2 for Channel A
D4
H3A
DO
CCD Horizontal Clock 3 for Channel A
D3
H4A
DO
CCD Horizontal Clock 4 for Channel A
B4
RG_A
DO
CCD Reset Gate Clock for Channel A
J2
DRVSS_A
P
Digital Driver Ground for Channel A
K3
DRVDD_A
P
Digital Driver Supply for Channel A
E3
HVSS_A
P
H1A to H4A Driver Ground for Channel A
E4
HVDD_A
P
H1A to H4A Driver Supply for Channel A
C3
RGVSS_A
P
RG_A Driver Ground for Channel A
C4
RGVDD_A
P
RG_A Driver Supply for Channel A
B3
TCVSS_A
P
Analog Ground for Channel A Timing Core
A4
TCVDD_A
P
Analog Supply for Channel A Timing Core
B1
AVSS_A
P
Analog Ground for Channel A
A2
AVDD_A
P
Analog Ground for Channel A
F2
DVSS_A
P
Digital Ground for Channel A
F1
DVDD_A
P
Digital Supply for Channel A
E2
VD_A
DI
Vertical Sync Pulse for Channel A
E1
HD_A
DI
Horizontal Sync Pulse for Channel A
B8
SL_B
DI
6-Wire Serial Load for Channel B
C8
SDATA_B
DI
6-Wire Serial Data for Channel B
D8
SCK_B
DI
6-Wire Serial Clock for Channel B
C7
REFT_B
AO
Reference Top Decoupling for Channel B (decouple with 1.0 μF to AVSS_B)
D7
REFB_B
AO
Reference Bottom Decoupling for Channel B (decouple with 1.0 μF to AVSS_B)
A7
CCDIN_B
AI
Analog Input for Channel B CCD Signal (connect through series 0.1 μF capacitor)
F10
H1B
DO
CCD Horizontal Clock 1 for Channel B
F9
H2B
DO
CCD Horizontal Clock 2 for Channel B
D10
H3B
DO
CCD Horizontal Clock 3 for Channel B
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