參數(shù)資料
型號(hào)： AD9942BBCZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 21/36頁(yè)
文件大小： 0K
描述： IC PROCESSOR SGNL 14B 100CSPBGA
標(biāo)準(zhǔn)包裝： 1
類型： CCD 信號(hào)處理器，14 位
應(yīng)用： 數(shù)碼相機(jī)
安裝類型： 表面貼裝
封裝/外殼： 100-LFBGA，CSPBGA
供應(yīng)商設(shè)備封裝： 100-CSBGA（9x9）
包裝： 托盤
AD9942
Rev. A | Page 28 of 36
CHANNEL A AND CHANNEL B
VARIABLE GAIN AMPLIFIER
The VGA stage provides a gain range of 0 dB to 18 dB, pro-
grammable with 9-bit resolution through the serial digital
interface. A minimum gain of 6 dB is needed to match a 1 V
input signal with the ADC full-scale range of 2 V.
The VGA gain curve follows a linear-in-dB characteristic. The
exact VGA gain can be calculated for any gain register value by
using the equation
Gain (dB) = (0.035 × VGAGAIN Code)
where the code range is 0 to 511.
20
0
2
4
6
8
10
12
14
16
18
0
50
100
150
200
250
300
350
400
450
500
05
24
0-
0
32
GAIN CODE (Decimal)
GA
IN
(
d
B
)
Figure 29. VGA Gain Curve
CHANNEL A AND CHANNEL B ADC
The AD9942 uses a high performance ADC architecture, opti-
mized for high speed and low power. Differential nonlinearity
(DNL) performance is typically better than 0.5 LSB. The ADC
uses a 2 V input range. See Figure 8 and Figure 9 for typical
linearity and noise performance plots for the AD9942.
CHANNEL A AND CHANNEL B CLPOB
The CLPOB loop is used to remove residual offsets in the signal
chain and to track low frequency variations in the CCD black
level. During the optical black (OB), or shielded, pixel interval
on each line, the ADC output is compared with a fixed black
level reference, selected by the user in the CLAMP LEVEL
register. The value can be programmed between 0 LSB and 255
LSB in 256 steps. The resulting error signal is filtered to reduce
noise, and the correction value is applied to the ADC input
through a digital-to-analog converter. Typically, the CLPOB
loop is turned on once per horizontal line, but this loop can be
updated more slowly to suit a particular application. If external
digital clamping is used during postprocessing, the AD9942
CLPOB can be disabled using Bit D2 in the OPRMODE register.
The CLAMP LEVEL register can be used to provide program-
mable offset adjustment even when the loop is disabled.
The CLPOB pulse should be placed during the CCD’s OB pixel
region. It is recommended that the CLPOB pulse duration be at
least 20 pixels wide to minimize clamp noise. Shorter pulse widths
can be used, but clamp noise might increase and the ability to
track low frequency variations in the black level is reduced. See
Blanking section and the Applications Information section for
timing examples.
CHANNEL A AND CHANNEL B
DIGITAL DATA OUTPUTS
The AD9942 digital output data is latched using the
DOUTPHASE register value, as shown in Figure 28. (Output
data timing is shown in Figure 19 and Figure 20.) It is also possible
to leave the output latches transparent, so that the data outputs
are valid immediately from the ADC. Programming the AFE
Control Register Bit D4 to 1 sets the output latches transparent.
The data outputs can also be disabled (three-stated) by setting
the AFE Control Register Bit D3 to 1.
The data output coding is typically straight binary, but the
coding can be changed to gray coding by setting the AFE
Control Register Bit D5 to 1.
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