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| 型號： | AD9942BBCZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 18/36頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PROCESSOR SGNL 14B 100CSPBGA |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | CCD 信號處理器，14 位 |
| 應(yīng)用： | 數(shù)碼相機(jī) |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-LFBGA，CSPBGA |
| 供應(yīng)商設(shè)備封裝： | 100-CSBGA（9x9） |
| 包裝： | 托盤 |
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AD9942
Rev. A | Page 25 of 36
Table 20. Channel A and Channel B HBLK Individual Sequence Parameters
Parameter
Length
(Bit)
Range
Description
HBLKMASK
1
High/low
Masking polarity for H1 for Sequences 0 to 3 (0 = low; 1 = high).
Toggle Position 1
12
0 to 4095 pixel locations
First toggle position within the line for Sequences 0 to 3.
Toggle Position 2
12
0 to 4095 pixel locations
Second toggle position within the line for Sequences 0 to 3.
Toggle Position 3
12
0 to 4095 pixel locations
Third toggle position within the line for Sequences 0 to 3.
Toggle Position 4
12
0 to 4095 pixel locations
Fourth toggle position within the line for Sequences 0 to 3.
Toggle Position 5
12
0 to 4095 pixel locations
Fifth toggle position within the line for Sequences 0 to 3.
Toggle Position 6
12
0 to 4095 pixel locations
Sixth toggle position within the line for Sequences 0 to 3.
Table 21. Channel A and Channel B Horizontal Sequence Control Registers for CLPOB, PBLK, and HBLK
Register
Length
(Bit)
Range
Description
SCP
12
0 to 4095 line numbers
CLPOB/PBLK/HBLK SCP to define Horizontal Regions 0 to 3.
SPTR
2
0 to 3 sequence numbers
Sequence pointer for Horizontal Regions 0 to 3.
Table 22. Channel A and Channel B External HBLK Register Parameters
Register
Length (Bit)
Range
Description
HBLKDIR
1
High/low
Specifies HBLK internally generated or externally supplied. 0 = internal; 1 = external.
HBLKPOL
1
High/low
External HBLK active polarity. 0 = active low; 1 = active high.
HBLKEXTMASK
1
High/low
External HBLK masking polarity. 0 = mask H1 low; 1 = mask H1 high.
H-COUNTER SYNCHRONIZATION
The H-counter reset occurs seven CLI cycles after the HD falling edge.
05
24
0-
02
9
0123
4567
89
10
11
12
14
15
012
3
H-COUNTER
RESET
VD_X
NOTES
1. INTERNAL H COUNTER IS RESET SEVEN CLI_X CYCLES AFTER THE HD_X FALLING EDGE (WHEN USING VDHDEDGE = 0).
2. TYPICAL TIMING RELATIONSHIP: CLI_X RISING EDGE IS COINCIDENT WITH HD_X FALLING EDGE.
HD_X
CLI_X
XX
X
H COUNTER
(PIXEL COUNTER)
XX
X
Figure 26. H-Counter Synchronization
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| AD9942BBCZRL | 功能描述:IC PROCESSOR SGNL 14B 100CSPBGA RoHS:是 類別:集成電路 (IC) >> 專用 IC 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝 |
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