參數(shù)資料
型號(hào)： AD9942BBCZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 17/36頁(yè)
文件大?。?/td> 0K
描述： IC PROCESSOR SGNL 14B 100CSPBGA
標(biāo)準(zhǔn)包裝： 1
類(lèi)型： CCD 信號(hào)處理器，14 位
應(yīng)用： 數(shù)碼相機(jī)
安裝類(lèi)型： 表面貼裝
封裝/外殼： 100-LFBGA，CSPBGA
供應(yīng)商設(shè)備封裝： 100-CSBGA（9x9）
包裝： 托盤(pán)
AD9942
Rev. A | Page 24 of 36
CHANNEL A AND CHANNEL B SPECIAL HBLK PATTERNS
Six toggle positions are available for HBLK. Typically, only two
of the toggle positions are used to generate the standard HBLK
interval. However, the additional toggle positions can be used to
generate special HBLK patterns, as shown in Figure 24. The
pattern in this example uses all six toggle positions to generate
two extra groups of pulses during the HBLK interval. By
changing the toggle positions, different patterns can be created.
HORIZONTAL SEQUENCE CONTROL
The AD9942 uses sequence change positions (SCPs) and
sequence pointers (SPTRs) to organize the individual horizontal
sequences. Up to four SCPs are available to divide the readout
into four separate regions, as shown in Figure 25. The SCP0 is
always hard-coded to Line 0, and SCP1 to SCP3 are register
programmable. During each region bounded by the SCP, the
SPTR registers designate which sequence is used by each signal.
CLPOB, PBLK, and HBLK each have a separate set of SCPs. For
example, CLPOBSCP1 defines Region 0 for CLPOB, and in that
region any of the four CLPOB sequences can be selected with
the CLPOBSPTR register. The next SCP defines a new region,
in which each signal can be assigned to a different individual se-
quence. The sequence control registers are detailed in Table 21.
HBLK
SPECIAL H-BLANK PATTERN IS CREATED USING MULTIPLE HBLK TOGGLE POSITIONS.
H1X/H3X
H2X/H4X
TOG1
TOG2
TOG3
TOG4
TOG5
TOG6
05
24
0-
0
27
Figure 24. Generating Special HBLK Patterns
UP TO FOUR INDIVIDUAL HORIZONTAL CLAMP AND BLANKING REGIONS MAY BE
PROGRAMMED WITHIN A SINGLE FIELD, USING THE SEQUENCE CHANGE POSITIONS.
SEQUENCE CHANGE OF POSITION 1
SEQUENCE CHANGE OF POSITION 2
SEQUENCE CHANGE OF POSITION 3
SINGLE FIELD (1 VD INTERVAL)
CLAMP AND PBLK SEQUENCE REGION 0
SEQUENCE CHANGE OF POSITION 0
(V COUNTER = 0)
CLAMP AND PBLK SEQUENCE REGION 3
CLAMP AND PBLK SEQUENCE REGION 2
CLAMP AND PBLK SEQUENCE REGION 1
05
24
0-
02
8
Figure 25. CLPOB and PBLK Sequence Flexibility
相關(guān)PDF資料
PDF描述
AD9944KCPZRL IC CCD SIGNAL PROCESSOR 32-LFCSP
AD9945KCPZRL7 IC CCD SIGNAL PROCESSOR 32-LFCSP
AD9948KCPZ IC CCD SIGNAL PROCESSOR 40-LFCSP
AD9949KCPZ IC CCD SIGNAL PROCESSOR 40-LFCSP
AD9951YSVZ IC DDS DAC 14BIT 1.8V 48-TQFP
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD9942BBCZRL 功能描述:IC PROCESSOR SGNL 14B 100CSPBGA RoHS:是 類(lèi)別:集成電路 (IC) >> 專用 IC 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類(lèi)型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類(lèi)型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝
AD9943 制造商:AD 制造商全稱:Analog Devices 功能描述:Complete 10-Bit and 12-Bit, 25 MHz CCD Signal Processors
AD9943KCP 制造商:Analog Devices 功能描述:AFE Video 1ADC 10-Bit 3V 32-Pin LFCSP EP 制造商:Rochester Electronics LLC 功能描述:10 BIT 25 MHZ LOW COST ANALOG FRONT END - Bulk
AD9943KCPRL 制造商:Analog Devices 功能描述:AFE Video 1ADC 10-Bit 3V 32-Pin LFCSP EP T/R
AD9943KCPZ 功能描述:IC CCD SIGNAL PROCESSOR 32-LFCSP RoHS:是 類(lèi)別:集成電路 (IC) >> 接口 - 傳感器和探測(cè)器接口 系列:- 其它有關(guān)文件:Automotive Product Guide 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:74 系列:- 類(lèi)型:觸控式傳感器 輸入類(lèi)型:數(shù)字 輸出類(lèi)型:數(shù)字 接口:JTAG，串行 電流 - 電源:100µA 安裝類(lèi)型:表面貼裝 封裝/外殼:20-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:20-TSSOP 包裝:管件
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*