參數(shù)資料
型號(hào)： AD9923ABBCZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 57/84頁(yè)
文件大?。?/td> 0K
描述： IC PROCESSOR CCD 12BIT 105CSPBGA
標(biāo)準(zhǔn)包裝： 1
類型： CCD 信號(hào)處理器，12 位
輸入類型： 邏輯
輸出類型： 邏輯
接口： 3 線串口
電流 - 電源： 20mA
安裝類型： 表面貼裝
封裝/外殼： 105-LFBGA，CSPBGA
供應(yīng)商設(shè)備封裝： 105-CSPBGA（8x8）
包裝： 托盤
AD9923A
Rev. A | Page 60 of 84
STANDBY MODE OPERATION
The AD9923A contains three standby modes to optimize the
overall power dissipation in various applications. Bits[1:0] of
Register 0x00 control the power-down state of the device:
STANDBY[1:0] = 00 = normal operation (full power)
STANDBY[1:0] = 01 = Standby 1 mode
STANDBY[1:0] = 2 = Standby 2 mode
STANDBY[1:0] = 3 = Standby 3 mode (lowest power)
Table 43 and Table 44 summarize the operation of each power-
down mode. Note that when OUTCONTROL = LO, it takes
priority over the Standby 1 and Standby 2 modes in determining
the digital output states, but Standby 3 mode takes priority over
OUTCONTROL. Standby 3 has the lowest power consumption,
and can shut down the crystal oscillator circuit between CLI
and CLO. If CLI and CLO are being used with a crystal to
generate the master clock, this circuit is powered down and
there is no clock signal. When returning the device from
Standby 3 mode to normal operation, reset the timing core at
least 500 μs after writing to the STANDBY register (Bits[1:0],
Address 0x00). This allows sufficient time for the crystal circuit
to settle. The vertical and shutter outputs can be programmed
to hold a specific value during the Standby 3 mode using
Register 0xE2, as detailed in Table 44. The vertical outputs can be
programmed to hold a specific value when OUTCONTROL =
low, or when in Standby 1 or Standby 2 mode, by using
Register 0xF3. The following list provides guidelines for the
mapping of the bits in these registers to the various vertical and
shutter outputs when the device is in one of the three standby
modes, or when OUTCONTROL = low.
Standby 3 mode takes priority over OUTCONTROL for
determining the output polarities.
These polarities assume OUTCONTROL = high, because
OUTCONTROL = low takes priority over Standby 1 and
Standby 2.
Standby 1 and Standby 2 set H and RG drive strength to
their minimum values (4.3 mA).
VD and HD default to High-Z status when in slave mode
regardless of standby mode or OUTCONTROL status.
This feature is useful during power-up if different polarities are
required by the V-driver and CCD to prevent damage.
It is important to note that when VDR_EN = 0 V, V1 to V13 are
at VM, and SUBCK is at VLL regardless of the state of the value
of the STANDBY and OUTCONTROL registers.
Table 43. Standby Mode Operation
I/O Block
Standby 3 (Default)1, 2
OUTCONTROL = LOW2
Standby 23, 4
Standby 13, 4
AFE
Off
No change
Off
Only REFT, REFB on
Timing Core
Off
No change
Off
On
CLO Oscillator
Off
No change
On
CLO
High
Running
HL
High-Z
Low
Low (4.3 mA)
H1
High-Z
Low
Low (4.3 mA)
H2
High-Z
High
High (4.3 mA)
H3
High-Z
Low
Low (4.3 mA)
H4
High-Z
High
High (4.3 mA)
RG
High-Z
Low
Low (4.3 mA)
Low
VDHDPOL value
Running
HD
Low
VDHDPOL value
Running
DCLK
Low
Running
Low
Running
D0 to D11
Low
1 To exit Standby 3, write 00 to STANDBY (Bits[1:0], Address 0x00), then reset the timing core after 500 μs to guarantee proper settling of the oscillator.
2 Standby 3 mode takes priority over OUTCONTROL for determining the output polarities.
3 These polarities assume OUTCONTROL = high, because OUTCONTROL = low takes priority over Standby 1 and Standby 2.
4 Standby 1 and Standby 2 set H and RG drive strength to their minimum values (4.3 mA).
5 VD and HD default to High-Z status when in slave mode regardless of Standby mode or OUTCONTROL status.
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