參數(shù)資料
型號(hào)： AD9923ABBCZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 30/84頁(yè)
文件大?。?/td> 0K
描述： IC PROCESSOR CCD 12BIT 105CSPBGA
標(biāo)準(zhǔn)包裝： 1
類(lèi)型： CCD 信號(hào)處理器，12 位
輸入類(lèi)型： 邏輯
輸出類(lèi)型： 邏輯
接口： 3 線串口
電流 - 電源： 20mA
安裝類(lèi)型： 表面貼裝
封裝/外殼： 105-LFBGA，CSPBGA
供應(yīng)商設(shè)備封裝： 105-CSPBGA（8x8）
包裝： 托盤(pán)
AD9923A
Rev. A | Page 36 of 84
Vertical Sensor Gate (Shift Gate) Patterns
In an interline CCD, the vertical sensor gates (VSG) are used to
transfer the pixel charges from the light sensitive image area
into the light shielded vertical registers. From the light shielded
vertical registers, the image is then read line by line using the
XV1 to XV13 vertical transfer pulses in conjunction with the
high speed horizontal clocks.
Table 20 summarizes the VSG pattern registers. The AD9923A
has eight VSG outputs, VSG1 to VSG8. Each output can be
assigned to one of eight programmed patterns by using the
SGPATSEL register. Each pattern is generated in a similar
manner as the V-pattern groups, with a programmable start
polarity (SGPOL), first toggle position (SGTOG1), and second
toggle position (SGTOG2). The active line where the VSG1 to
VSG8 pulses occur is programmable using the SGACTLINE1
and SGACTLINE2 registers. Additionally, any of the VSG1 to
VSG8 pulses can be individually disabled using the SGMASK
register. The individual masking allows all SG patterns to be
preprogrammed, and the appropriate pulses for each field can
be separately enabled. For maximum flexibility, the SGPATSEL,
SGMASK, and SGACTLINE registers are separately programmable
for each field. More detail is given in the Complete Field:
Additionally, there is the SGMASK_BYP register (Address 0x59)
that overrides SG masking in the field registers. The SGMASK_BYP
register allows sensor gate masking to be changed without
modifying the field register values. The SGMASK_BYP register
is SCK updated; therefore, the new SG-masking values update
immediately.
Table 20. VSG Pattern Registers1
Register
Length
(Bits)
Range
Description
SGPOL
1
High/low
Sensor gate starting polarity for SG patterns 0 to 7.
SGTOG1
13
0 to 8191 pixel
location
First toggle position for SG patterns 0 to 7.
SGTOG2
13
0 to 8191 pixel
location
Second toggle position for SG patterns 0 to 7.
SGMASK_BYP
8
High/low for
each VSG
SGMASK Bypass. This register overrides the SGMASK values in each field register. One
bit for each output, where Bit[0] is for VSG1 output and Bit 7 is for VSG8 output.
0 = active.
1 = mask output.
SGMASK_BYP_EN
1
0 or 1
1: enables SGMASK bypass.
VD
HD
PROGRAMMABLE SETTINGS FOR EACH PATTERN:
1START POLARITY OF PULSE.
2FIRST TOGGLE POSITION.
3SECOND TOGGLE POSITION.
4ACTIVE LINE FOR VSG PULSES WITHIN THE FIELD (PROGRAMMABLE IN THE FIELD REGISTER, NOT FOR EACH PATTERN).
VSG PATTERNS
1 See field registers in Table 17.
4
12
3
0
55
86
-04
9
Figure 50. Vertical Sensor Gate Pulse Placement
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