參數(shù)資料
型號(hào)： AD9923ABBCZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 52/84頁(yè)
文件大小： 0K
描述： IC PROCESSOR CCD 12BIT 105CSPBGA
標(biāo)準(zhǔn)包裝： 1
類型： CCD 信號(hào)處理器，12 位
輸入類型： 邏輯
輸出類型： 邏輯
接口： 3 線串口
電流 - 電源： 20mA
安裝類型： 表面貼裝
封裝/外殼： 105-LFBGA，CSPBGA
供應(yīng)商設(shè)備封裝： 105-CSPBGA（8x8）
包裝： 托盤(pán)
AD9923A
Rev. A | Page 56 of 84
Optical Black Clamp
The optical black clamp loop removes residual offsets in the
signal chain and tracks low frequency variations in the CCD
black level. During the optical black (shielded) pixel interval on
each line, the ADC output is compared with a fixed black level
reference, selected by the user in the CLAMPLEVEL register.
The value can be programmed between 0 LSB and 255 LSB in
1023 steps. The resulting error signal is filtered to reduce noise
and the correction value is applied to the ADC input through a
DAC. Normally, the optical black clamp loop is turned on once
per horizontal line, but this loop can be updated more slowly to
suit a particular application. If external digital clamping is used
during postprocessing, the AD9923A optical black clamping
can be disabled using the CLPENABLE register (Address 0x00,
Bit D2). Even though the loop is disabled, the CLAMPLEVEL
register can still be used to provide programmable offset
adjustment.
The CLPOB pulse should be placed during the CCD optical
black pixels. It is recommended that the CLPOB pulse duration
is at least 20 pixels wide to minimize clamping noise. Shorter
pulse widths can be used, but clamping noise might increase,
reducing the ability to track low frequency variations in the
black level. See the Horizontal Clamping and Blanking section
for timing examples.
Digital Data Outputs
The digital output data is latched using the DOUTPHASE
register value, as shown in Figure 73. Output data timing is shown
in Figure 21 and Figure 22. It is also possible to leave the output
latches transparent, so that the data outputs from the ADC are
immediately valid. Programming the DOUTLATCH register,
Bit D1 to 1 sets the output latches transparent. The data outputs
can also be disabled (three-stated) by setting the DOUTDISABLE
Register 0x01, Bit D0 to 1.
The DCLK output can be used for external latching of the data
outputs. By default, the DCLK output tracks the value of the
DOUTPHASE register. By changing the DCLKMODE register,
the DCLK output can be held at a fixed phase, and the
DOUTPHASE register value is ignored.
To optimize the delay between the DCLK rising edge and the
data output transition, the DOUTDELAY register is used. By
default, there is approximately 8 ns of delay from the rising edge
of DCLK to the transition of the data outputs. See the High
Speed Timing Generation section for more information.
Switching the data outputs can couple noise into the analog
signal path. To minimize switching noise, set the DOUTPHASE
register to the same edge as the SHP sampling location, or up to
11 edges after the SHP sampling location. Other settings can
produce good results but require experimentation. It is
recommended that the DOUTPHASE location not occur
between the SHD sampling location and 11 edges after the SHD
location. For example, if SHDLOC = 0, set DOUTPHASE to an
edge location of 12 or greater. If adjustable phase is not required
for the data outputs, the output latch can be left transparent
using Register 0x01, Bit D1.
Data output coding is normally straight binary, but can be
changed to gray coding by setting the GRAYEN Register 0x01,
Bit D2 to 1.
Recommended Power-Up Sequence for Master Mode
When the AD9923A is powered up, the following sequence is
recommended (see Figure 75):
1.
Turn on the +3 V power supplies for the AD9923A, and
start the master clock (CLI).
2.
Turn on the V-driver supplies (VH and VL). There are no
restrictions on the order in which VH and VL are turned on.
3.
Reset the internal AD9923A registers by writing 1 to the
SW_RST register (Address 0x10).
4.
Load the required registers to configure the required
VPAT group, V-sequence, field timing information, high
speed timing, horizontal timing, and shutter timing
information.
5.
To place the part into normal power operation, write 0x04
to the AFE STANDBY register (Bits[1:0], Address 0x00)
and 0x60 to TEST3 Register 0xEA. If the CLO output is
being used to drive a crystal, also power up the CLO
oscillator by writing 1 to Register 0x16.
6.
By default, the internal timing core is held in a reset state
with TGCORE_RSTB register = 0. Write 1 to the
TGCORE_RSTB register (Address 0x15) to start the
internal timing core operation. If a 2× clock is used for the
CLI input, set the CLIDIVIDE register (Address 0x30) to
1 before resetting the timing core. It is important to wait
at least 500 μs after starting the master clock (CLI) before
resetting the timing core, especially if using a crystal or
crystal oscillator.
7.
Configure the AD9923A for master mode timing by
writing 1 to the MASTER register (Address 0x20).
8.
Bring the VDR_EN signal high to +3 V to enable the
V-driver outputs. If VDR_EN = 0 V, all V-driver outputs =
VM, and SUBCK = VLL.
9.
Write 1 to the OUTCONTROL register (Address 0x11).
This allows the outputs to become active after the next
SYNC rising edge.
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