參數(shù)資料
型號: AD9923ABBCZ
廠商: Analog Devices Inc
文件頁數(shù): 24/84頁
文件大?。?/td> 0K
描述: IC PROCESSOR CCD 12BIT 105CSPBGA
標(biāo)準(zhǔn)包裝: 1
類型: CCD 信號處理器,12 位
輸入類型: 邏輯
輸出類型: 邏輯
接口: 3 線串口
電流 - 電源: 20mA
安裝類型: 表面貼裝
封裝/外殼: 105-LFBGA,CSPBGA
供應(yīng)商設(shè)備封裝: 105-CSPBGA(8x8)
包裝: 托盤
AD9923A
Rev. A | Page 30 of 84
Masking Using Freeze/Resume Registers
As shown in Figure 42 and Figure 43, the FREEZE/RESUME
registers are used to temporarily mask the XV outputs. The
pixel locations to start (FREEZE) and end (RESUME) the
masking create an area in which the vertical toggle positions are
ignored. At the pixel location specified in the FREEZE register,
the XV outputs are held static at their current dc state, high or
low. The XV outputs are held until the internal pixel counter
reaches the pixel location specified by the RESUME register, at
which point the signals continue with any remaining toggle
positions.
Two sets of FREEZE/RESUME registers are provided, allowing
the vertical outputs to be interrupted twice in the same line. The
FREEZE and RESUME positions are enabled using the VMASK
register.
It is not recommended to use FREEZE/RESUME at the same
time as the SWEEP function.
XV1
XV13
HD
NO MASKING AREA
0
55
86
-04
1
Figure 42. Not Using FREEZE/RESUME
XV1
XV13
HD
NOTES
1. ALL TOGGLE POSITIONS WITHIN THE FREEZE-RESUME MASKING AREA ARE IGNORED. H-COUNTER CONTINUES TO COUNT DURING MASKING.
2. TWO SEPARATE MASKING AREAS ARE AVAILABLE FOR EACH GROUP A, USING FREEZE1/RESUME1 AND FREEZE2/RESUME2 REGISTERS.
MASKING AREA
FOR GROUP A
FREEZE
RESUME
05
58
6-
04
2
Figure 43. Using FREEZE/RESUME
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