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| 型號： | AD9858BSVZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 30/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DDS DAC 10BIT 1GSPS 100-TQFP |
| 產品培訓模塊： | Direct Digital Synthesis Tutorial Series (1 of 7): Introduction Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator |
| 設計資源： | Low Jitter Sampling Clock Generator for High Performance ADCs Using AD9958/9858 and AD9515 (CN0109) |
| 標準包裝： | 1 |
| 分辨率（位）： | 10 b |
| 主 fclk： | 1GHz |
| 調節(jié)字寬（位）： | 32 b |
| 電源電壓： | 3.14 V ~ 3.47 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-TQFP 裸露焊盤 |
| 供應商設備封裝： | 100-TQFP-EP（14x14） |
| 包裝： | 托盤 |
| 產品目錄頁面： | 552 (CN2011-ZH PDF) |
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AD9858
Rev. C | Page 7 of 32
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
84
83
82
81
80
79
78
77
76
95
94
93
92
91
90
89
88
87
86
85
100
999897
96
26
28
29
30
31
32
33
38
39
34
35
36
37
42
40
41
43
44
45
46
47
48
49
50
13
DVDD
D7
D6
D5
D4
DGND
DVDD
D3
D2
D1
D0
ADDR5
ADDR4
ADDR3
RD/CS
DVDD
DG
ND
DV
D
DV
D
AG
ND
AG
ND
AV
D
RE
F
CL
K
AV
D
RE
F
CL
K
AV
D
AV
D
AG
ND
AG
ND
AV
D
AG
ND
AG
ND
AG
ND
AV
D
AV
D
LO
AV
D
AG
ND
AV
D
AG
ND
PS1
SYN
C
L
K
FU
D
PS0
DG
ND
DG
ND
RE
S
E
T
DV
DD
DV
DD
AV
DD
SPS
EL
EC
T
AG
ND
AV
DD
AV
DD
AG
ND
IO
U
T
AG
ND
IO
U
T
IO
U
T
AG
ND
IO
U
T
DACI
S
E
T
AV
DD
DACBP
NC
ADDR2/IORESET
ADDR1/SDO
ADDR0/SDIO
WR/SCLK
DVDD
DGND
AVDD
NC
AGND
AVDD
DIV
AVDD
AGND
CPGND
CPVDD
CP
CPFL
CPGND
CPVDD
CPISET
RF
AGND
NC
PFD
IF
AD9858
TOP VIEW
(Not to Scale)
27
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
75
74
73
72
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70
69
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51
NOTES
1. NC = NO CONNECT.
2. THE TQFP_EP (THERMAL SLUG) MUST BE ATTACHED TO THE GROUND PLANE OR SOME OTHER LARGE
METAL MASS FOR THERMAL TRANSFER. FAILURE TO DO SO MAY CAUSE EXCESSIVE DIE TEMPERATURE
RISE AND DAMAGE TO THE DEVICE.
03
16
6-
0
44
Figure 2. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
I/O
Description
1 to 4, 9 to 12
D7 to D0
I
Parallel Port Data. The functionality of these pins is valid only when the I/O port is configured as
a parallel port.
5, 6, 21, 28, 95, 96
DGND
Digitial Ground.
7, 8, 20, 23 to 27,
93, 94
DVDD
Digital Supply Voltage.
13 to 18
ADDR5 to
ADDR0
I
When the I/O port is configured as a parallel port, these pins serve as a 6-bit address select for
accessing the on-chip registers (see the IORESET, SDO, and SDIO pins for the serial port mode).
16
IORESET
I
This is valid for serial programming mode only. Active high input signal that resets the serial I/O
bus controller. It serves as a means of recovering from an unresponsive serial bus caused by
an improper programming protocol. Asserting an I/O reset does not affect the contents of
previously programmed registers, nor does it invoke their default values.
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