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參數(shù)資料
| 型號： | AD9858BSVZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 13/32頁 |
| 文件大小： | 0K |
| 描述： | IC DDS DAC 10BIT 1GSPS 100-TQFP |
| 產(chǎn)品培訓模塊： | Direct Digital Synthesis Tutorial Series (1 of 7): Introduction Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator |
| 設(shè)計資源： | Low Jitter Sampling Clock Generator for High Performance ADCs Using AD9958/9858 and AD9515 (CN0109) |
| 標準包裝： | 1 |
| 分辨率（位）： | 10 b |
| 主 fclk： | 1GHz |
| 調(diào)節(jié)字寬（位）： | 32 b |
| 電源電壓： | 3.14 V ~ 3.47 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-TQFP 裸露焊盤 |
| 供應商設(shè)備封裝： | 100-TQFP-EP（14x14） |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 552 (CN2011-ZH PDF) |
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AD9858
Rev. C | Page 20 of 32
I/O Port Functionality
The I/O port can operate in either serial or parallel programming
mode. Mode selection is accomplished via the SPSELECT pin.
The ability to read back the contents of a register is provided in
both modes to facilitate the debug process during the user’s
prototyping phase of a design. In either mode, however, the
reading back of profile registers requires that the profile select
pins (PS0 and PS1) be configured to select the desired register
bank. When reading a register that resides in one of the profiles,
the register address acts as an offset to select one of the registers
among the group of registers defined by the profile. The profile
select pins control the base address of the register bank and
select the appropriate register grouping.
Parallel Programming Mode
In parallel programming mode, the I/O port makes use of eight
bidirectional data pins (D7 to D0), six address input pins (ADDR5
to ADDR0), a read input pin (RD), and a write input pin (WR).
A register is selected by providing the proper address combination
as defined in the register map (see
). Read or write
functionality is invoked by pulsing the appropriate pin (
RD or
WR); the two operations are mutually exclusive. The read or write
data is transported on the D7 to D0 pins. The correlation between
the D7 to D0 data bits and their functionality at a specific register
address is detailed in the register map (see
) and register
bit description.
Parallel I/O operation allows write access to each byte of any
register in the I/O buffer memory in a single I/O operation.
Readback capability is slower than write capability. It is intended as
a low speed function for debug purposes. Timing for both write
and read cycles is depicted in Figure 35 and Figure 36.
A3
A1
A2
D3
D1
D2
tWRHIGH
tWRLOW
tAHU
tDHU
tDSU
tASU
tWR
tASU
tDSU
tAHU
tDHU
tWRLOW
tWRHIGH
tWR
SPECIFICATION
3ns
3.5ns
0ns
3ns
6ns
9ns
VALUE
ADDRESS SETUP TIME TO WR SIGNAL ACTIVE
DATA SETUP TIME TO WR SIGNAL INACTIVE
ADDRESS HOLD TIME TO WR SIGNAL INACTIVE
DATA HOLD TIME TO WR SIGNAL INACTIVE
WR SIGNAL MINIMUM LOW TIME
WR SIGNAL MINIMUM HIGH TIME
WR SIGNAL MINIMUM PERIOD
DESCRIPTION
D[7:0]
ADDR[5:0]
WR
03
16
6-
03
8
Figure 35. I/O Port Write Cycle Timing (Parallel)
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