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參數(shù)資料
| 型號： | AD9858BSVZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 27/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DDS DAC 10BIT 1GSPS 100-TQFP |
| 產(chǎn)品培訓(xùn)模塊： | Direct Digital Synthesis Tutorial Series (1 of 7): Introduction Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator |
| 設(shè)計資源： | Low Jitter Sampling Clock Generator for High Performance ADCs Using AD9958/9858 and AD9515 (CN0109) |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 分辨率（位）： | 10 b |
| 主 fclk： | 1GHz |
| 調(diào)節(jié)字寬（位）： | 32 b |
| 電源電壓： | 3.14 V ~ 3.47 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-TQFP 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 100-TQFP-EP（14x14） |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 552 (CN2011-ZH PDF) |
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AD9858
Rev. C | Page 4 of 32
Parameter
Temp
Test Level
Min
Typ
Max
Unit
OUTPUT PHASE NOISE CHARACTERISTICS
(AT 100 MHz IOUT With 700 MHz REFCLK)
At 100 Hz Offset
Full
V
–125
dBc/Hz
At 1 kHz Offset
Full
V
–140
dBc/Hz
At 10 kHz Offset
Full
V
–148
dBc/Hz
At 100 kHz Offset
Full
V
–150
dBc/Hz
At 1 MHz Offset
Full
V
–150
dBc/Hz
At 10 MHz Offset
Full
V
–150
dBc/Hz
PHASE DETECTOR AND CHARGE PUMP
Phase Detector Frequency
Full
VI
150
MHz
Phase Detector Frequency (Divide-by-4 Enabled)3
Full
VI
400
MHz
Charge Pump Sink and Source Current4
Full
VI
4
mA
Fast Lock Current (Acquisition Only)
Full
VI
7
mA
Open-Loop Current (Acquisition Only)
Full
VI
30
mA
Sink and Source Current Absolute Accuracy5
Full
V
2.5
%
Sink and Source Current Matching5
Full
V
1
%
Full
IV
–15
0
dBm
Input Impedance PDIN and DIVIN (Single-Ended)
Full
V
1
kΩ
Phase Noise @ 100 MHz Input Frequency
At 10 kHz Offset
Full
V
110
dBc/Hz
At 100 kHz Offset
Full
V
140
dBc/Hz
At 1 MHz Offset
Full
V
148
dBc/Hz
Charge Pump Output Range7
Full
V
CPVDD
V
MIXER
IFOUT8
Full
V
400
MHz
fRF
Full
VI
2
GHz
fLO
Full
VI
2
GHz
Conversion Gain
Full
VI
0.0
3.5
dB
LO Level
Full
VI
–10
+5
dBm
RF Level
Full
VI
–20
dBm
Input IP3
Full
VI
5
9
dBm
1 dB Input Compression Power9
Full
VI
–3
dBm
Input Impedance (Single-Ended)
LO
Full
V
1
kΩ
RF
Full
V
1
kΩ
CMOS LOGIC INPUTS
Logic 1 Voltage
Full
VI
2.0
V
Logic 0 Voltage
Full
VI
0.8
V
Logic 1 Current
Full
VI
12
μA
Logic 0 Current
Full
VI
12
μA
Input Capacitance
Full
V
3
pF
CMOS LOGIC OUTPUTS (1 mA LOAD)
Logic 1 Voltage
Full
VI
2.8
V
Logic 0 Voltage
Full
VI
0.4
V
POWER DISSIPATION
PDISS (Worst-Case Conditions—Everything on
PFD Input Frequency 150 MHz)
Full
VI
2
2.5
W
PDISS (DAC and DDS Core Only Worst-Case)
Full
VI
1.7
2
W
PDISS (Power-Down Mode)
Full
VI
65
100
mW
PDISS Mixer Only
Full
VI
60
75
mW
PDISS PFD and CP (at 100 MHz) Only
Full
VI
350
435
mW
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相關(guān)代理商/技術(shù)參數(shù) |
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| AD9858FDPCB | 制造商:AD 制造商全稱:Analog Devices 功能描述:1 GSPS Direct Digital Synthesizer |
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| AD9858TLPCB | 制造商:AD 制造商全稱:Analog Devices 功能描述:1 GSPS Direct Digital Synthesizer |
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