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參數(shù)資料
| 型號： | AD9858BSVZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 21/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DDS DAC 10BIT 1GSPS 100-TQFP |
| 產(chǎn)品培訓模塊： | Direct Digital Synthesis Tutorial Series (1 of 7): Introduction Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator |
| 設計資源： | Low Jitter Sampling Clock Generator for High Performance ADCs Using AD9958/9858 and AD9515 (CN0109) |
| 標準包裝： | 1 |
| 分辨率（位）： | 10 b |
| 主 fclk： | 1GHz |
| 調(diào)節(jié)字寬（位）： | 32 b |
| 電源電壓： | 3.14 V ~ 3.47 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-TQFP 裸露焊盤 |
| 供應商設備封裝： | 100-TQFP-EP（14x14） |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 552 (CN2011-ZH PDF) |
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AD9858
Rev. C | Page 28 of 32
EVALUATION BOARDS
The AD9858 has three different evaluation board designs. The
first design is the traditional DDS evaluation board (see Figure 38).
In this design, the DDS is clocked and the output is taken
directly from the DAC. The analog mixer and PLL blocks are
made available for separate evaluation.
The second design is a fractional divide loop (see Figure 39).
This evaluation board was designed to incorporate the DDS, the
phase frequency detector, and the charge pump. In this
application, the DDS is used in a PLL loop. Unlike a fixed
divider used in traditional PLL loops, the output signal is
divided and fed back to the phase frequency detector by the
DDS. To do this, the output signal of the PLL loop is fed to the
DDS as REFCLK. The DDS is programmed to match the
reference input frequency. Because the DDS output frequency
can take on 232 potential values between 0 Hz and one-half of
the PLL loop output frequency, this enables frequency
resolution on the order of 470 MHz, assuming a PLL loop
output frequency of 2 GHz.
The third design is a translation loop or offset loop (see Figure 37).
In this design, the analog mixer is incorporated into the feedback
path of the loop. This allows direct up-conversion to the
transmission frequency.
The three evaluation boards have separate schematics, BOMs, and
instructions. See www.analog.com/dds for more information.
Table 13. Evaluation Boards for the AD9858
Model
Description
AD9858/PCBZ
AD9858 Frequency Synthesizer Board
AD9858/FDPCB
AD9858 Fractional Divide Loop Frequency
Synthesizer Board
AD9858/TLPCBZ
AD9858 Translation Loop Frequency
Synthesizer Board
相關PDF資料 |
PDF描述 |
|---|---|
| AD9859YSVZ-REEL7 | IC DDS DAC 10BIT 400MSPS 48TQFP |
| AD9880KSTZ-100 | IC INTERFACE/HDMI 100MHZ 100LQFP |
| AD9882KSTZ-140 | IC INTERFACE/DVI 100MHZ 100LQFP |
| AD9883ABSTZ-RL140 | IC INTERFACE FLAT 140MHZ 80LQFP |
| AD9887AKSZ-100 | IC INTRFACE ANALOG/DVI 160-MQFP |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AD9858FDPCB | 制造商:AD 制造商全稱:Analog Devices 功能描述:1 GSPS Direct Digital Synthesizer |
| AD9858PCB | 制造商:AD 制造商全稱:Analog Devices 功能描述:1 GSPS Direct Digital Synthesizer |
| AD9858TLPCB | 制造商:AD 制造商全稱:Analog Devices 功能描述:1 GSPS Direct Digital Synthesizer |
| AD9858XSV | 制造商:Analog Devices 功能描述: |
| AD9859 | 制造商:AD 制造商全稱:Analog Devices 功能描述:400 MSPS, 10-Bit, 1.8 V CMOS Direct Digital Synthesizer |
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