參數(shù)資料
型號： AD9854ASTZ
廠商： Analog Devices Inc
文件頁數(shù)： 27/52頁
文件大?。?/td> 0K
描述： IC DDS QUADRATURE CMOS 80-LQFP
產(chǎn)品培訓(xùn)模塊： Direct Digital Synthesis Tutorial Series (1 of 7): Introduction
Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action
Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter
Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction
Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter
Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator
標(biāo)準(zhǔn)包裝： 1
分辨率（位）： 12 b
主 fclk： 300MHz
調(diào)節(jié)字寬（位）： 48 b
電源電壓： 3.14 V ~ 3.47 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 80-LQFP
供應(yīng)商設(shè)備封裝： 80-LQFP（14x14）
包裝： 托盤
產(chǎn)品目錄頁面： 552 (CN2011-ZH PDF)
配用： AD9854/PCBZ-ND - BOARD EVAL FOR AD9854
AD9854
Rev. E | Page 33 of 52
Table 8. Register Layout1
AD9854 Register Layout
Parallel
Address
(Hex)
Serial
Address
(Hex)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Default
Value
(Hex)
00
0
Phase Adjust Register 1 <13:8> (Bits 15, 14, don’t care)
Phase 1
00
01
Phase Adjust Register 1 <7:0>
00
02
1
Phase Adjust Register 2 <13:8> (Bits 15, 14, don’t care)
Phase 2
00
03
Phase Adjust Register 2 <7:0>
00
04
2
Frequency Tuning Word 1 <47:40>
Freq 1
00
05
Frequency Tuning Word 1 <39:32>
00
06
Frequency Tuning Word 1 <31:24>
00
07
Frequency Tuning Word 1 <23:16>
00
08
Frequency Tuning Word 1 <15:8>
00
09
Frequency Tuning Word 1 <7:0>
00
0A
3
Frequency Tuning Word 2 <47:40>
0B
Frequency Tuning Word 2 <39:32>
00
0C
Frequency Tuning Word 2 <31:24>
00
0D
Frequency Tuning Word 2 <23:16>
00
0E
Frequency Tuning Word 2 <15:8>
00
0F
Frequency Tuning Word 2 <7:0>
00
10
4
Delta frequency word <47:40>
00
11
Delta frequency word <39:32>
00
12
Delta frequency word <31:24>
00
13
Delta frequency word <23:16>
00
14
Delta frequency word <15:8>
00
15
Delta frequency word <7:0>
00
16
5
Update clock <31:24>
00
17
Update clock <23:16>
00
18
Update clock <15:8>
00
19
Update clock <7:0>
40
1A
6
Ramp rate clock <19:16> (Bits 23, 22, 21, 20, don’t care)
00
1B
Ramp rate clock <15:8>
00
1C
Ramp rate clock <7:0>
00
1D
7
Don’t
care
CR [31]
Don’t
care
Don’t
care
Comp
PD
Reserved,
always low
QDAC PD
DAC PD
DIG PD
10
1E
Don’t
care
PLL
range
Bypass
PLL
Ref
Mult 4
Ref Mult 3
Ref Mult 2
Ref
Mult 1
Ref Mult 0
64
1F
CLR
ACC 1
CLR
ACC 2
Triangle
SRC
QDAC
Mode 2
Mode 1
Mode 0
Internal/external
update clock
01
20
Don’t
care
Bypass
inv sinc
OSK EN
OSK
INT
Don’t care
LSB first
SDO active CR [0]
20
21
8
Output shaped keying I multiplier <11:8> (Bits 15, 14, 13, 12 don’t care)
00
22
Output shaped keying I multiplier <7:0>
00
23
9
Output shaped keying Q multiplier <11:8> (Bits 15, 14, 13, 12 don’t care)
00
24
Output shaped keying Q multiplier <7:0>
00
25
A
Output shaped keying ramp rate <7:0>
80
26
B
QDAC <11:8> (Bits 15, 14, 13, 12 don’t care)
00
27
QDAC <7:0> (data is required to be in twos complement format)
1 The shaded sections comprise the control register.
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