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參數(shù)資料
| 型號(hào)： | AD9854ASTZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 13/52頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DDS QUADRATURE CMOS 80-LQFP |
| 產(chǎn)品培訓(xùn)模塊： | Direct Digital Synthesis Tutorial Series (1 of 7): Introduction Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 分辨率（位）： | 12 b |
| 主 fclk： | 300MHz |
| 調(diào)節(jié)字寬（位）： | 48 b |
| 電源電壓： | 3.14 V ~ 3.47 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 80-LQFP |
| 供應(yīng)商設(shè)備封裝： | 80-LQFP（14x14） |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 552 (CN2011-ZH PDF) |
| 配用： | AD9854/PCBZ-ND - BOARD EVAL FOR AD9854 |
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AD9854
Rev. E | Page 20 of 52
000 (SINGLE TONE)
MODE
F1
TW1
000 (DEFAULT)
0
F1
0
F
RE
Q
UE
NC
Y
MASTER RESET
I/O UD CLK
00
63
6-
0
35
Figure 35. Default State to User-Defined Output Transition
As with all Analog Devices DDS devices, the value of the
frequency tuning word is determined by
FTW = (Desired Output Frequency × 2N)/SYSCLK
where:
N is the phase accumulator resolution (48 bits in this instance).
Desired Output Frequency is expressed in hertz.
FTW (frequency tuning word) is a decimal number.
After a decimal number has been calculated, it must be rounded
to an integer and then converted to binary format, that is, a
series of 48 binary-weighted 1s and 0s. The fundamental sine
wave DAC output frequency range is from dc to one-half SYSCLK.
Changes in frequency are phase continuous, meaning that the
first sampled phase value of the new frequency is referenced from
the time of the last sampled phase value of the previous frequency.
The I and Q DACs of the AD9854 are always 90° out of phase.
The 14-bit phase registers do not independently adjust the
phase of each DAC output. Instead, both DACs are affected
equally by a change in phase offset.
The single-tone mode allows the user to control the following
signal qualities:
Output frequency to 48-bit accuracy
Output amplitude to 12-bit accuracy
Fixed, user-defined amplitude control
Variable, programmable amplitude control
Automatic, programmable, single-pin-controlled
on/off output shaped keying
Output phase to 14-bit accuracy
These qualities can be changed or modulated via the 8-bit
parallel programming port at a 100 MHz parallel byte rate or at
a 10 MHz serial rate. Incorporating this attribute permits FM,
AM, PM, FSK, PSK, and ASK operation in single-tone mode.
Unramped FSK (Mode 001)
When the unramped FSK mode is selected, the output frequency of
the DDS is a function of the values loaded into Frequency Tuning
Word Register 1 and Frequency Tuning Word Register 2 and the
logic level of Pin 29 (FSK/BPSK/HOLD). A logic low on Pin 29
chooses F1 (Frequency Tuning Word 1, Parallel Address 4 hex to
Parallel Address 9 hex), and a logic high chooses F2 (Frequency
Tuning Word 2, Parallel Register Address A hex to Parallel
Register Address F hex). Changes in frequency are phase
continuous and are internally coincident with the FSK data pin
(Pin 29); however, there is deterministic pipeline delay between
the FSK data signal and the DAC output. (Refer to the pipeline
delays in Table 1.)
The unramped FSK mode, shown in Figure 36, represents
traditional FSK, radio teletype (RTTY), or teletype (TTY)
transmission of digital data. FSK is a very reliable means of
digital communication; however, it makes inefficient use of
the bandwidth in the RF spectrum. Ramped FSK, shown in
Figure 37, is a method of conserving bandwidth.
Ramped FSK (Mode 010)
This mode is a method of FSK whereby changes from F1 to F2
are not instantaneous, but are accomplished in a frequency sweep
or ramped fashion (the ramped notation implies that the sweep
is linear). Although linear sweeping, or frequency ramping, is
easily and automatically accomplished, it is only one of many
schemes. Other frequency transition schemes can be
implemented by changing the ramp rate and ramp step size on
the fly in a piecewise fashion.
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| AD9854ASVZ | 制造商:Analog Devices 功能描述:CMOS 300 MSPS QUADRATURE COMPLETE DDS 制造商:Analog Devices 功能描述:CMOS 300 MSPS QUADRATURE COMPLETE DDS - Trays 制造商:Analog Devices 功能描述:SYNTHESIZER 制造商:Analog Devices 功能描述:Complete DDS Quadrature 300MSPS TQFP80 |
| AD9854PCB | 制造商:AD 制造商全稱:Analog Devices 功能描述:CMOS 300 MSPS Quadrature Complete DDS |
| AD9856 | 制造商:AD 制造商全稱:Analog Devices 功能描述:CMOS 200 MHz Quadrature Digital Upconverter |
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| AD9856AST | 制造商:Analog Devices 功能描述:Digital Up Converter 48-Pin LQFP Tray 制造商:Analog Devices 功能描述:IC MODULATOR DIGITAL |
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