參數資料
| 型號： | AD9854ASTZ |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 21/52頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DDS QUADRATURE CMOS 80-LQFP |
| 產品培訓模塊： | Direct Digital Synthesis Tutorial Series (1 of 7): Introduction Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator |
| 標準包裝： | 1 |
| 分辨率（位）： | 12 b |
| 主 fclk： | 300MHz |
| 調節(jié)字寬（位）： | 48 b |
| 電源電壓： | 3.14 V ~ 3.47 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 80-LQFP |
| 供應商設備封裝： | 80-LQFP（14x14） |
| 包裝： | 托盤 |
| 產品目錄頁面： | 552 (CN2011-ZH PDF) |
| 配用： | AD9854/PCBZ-ND - BOARD EVAL FOR AD9854 |
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AD9854
Rev. E | Page 28 of 52
h, it
s phase
put carrier.
2.
o Phase
ster 2.
4.
Activate the I/O update clock when ready.
ct
1
using the serial or high speed parallel programming bus.
Continue chirp by immediately returning to the beginning
frequency (F1) in a sawtooth fashion, and then repeating the
previous chirp process using the CLR ACC1 control bit.
An automatic, repeating chirp can be set up by using the
32-bit update clock to issue the CLR ACC1 command at
precise time intervals. Adjusting the timing intervals or
changing the delta frequency word changes the chirp
range. It is incumbent upon the user to balance the chirp
duration and frequency resolution to achieve the proper
frequency range.
BPSK (Mode 100)
Binary, biphase, or bipolar phase shift keying is a means to
rapidly select between two preprogrammed 14-bit output phase
offsets that equally affect both the I and Q outputs of the
AD9854. The logic state of Pin 29, the BPSK pin, controls the
selection of Phase Adjust Register 1 or Phase Adjust Register 2.
When low, Pin 29 selects Phase Adjust Register 1; when hig
selects Phase Adjust Register 2. Figure 48 illustrate
changes made to four cycles of an out
Basic BPSK Programming Steps
1.
Program a carrier frequency into Frequency Tuning Word 1.
Program the appropriate 14-bit phase words int
Adjust Register 1 and Phase Adjust Regi
3.
Attach the BPSK data source to Pin 29.
Note that for higher-order PSK modulation, the user can sele
the single-tone mode and program Phase Adjust Register
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相關代理商/技術參數 |
參數描述 |
|---|---|
| AD9854ASVZ | 制造商:Analog Devices 功能描述:CMOS 300 MSPS QUADRATURE COMPLETE DDS 制造商:Analog Devices 功能描述:CMOS 300 MSPS QUADRATURE COMPLETE DDS - Trays 制造商:Analog Devices 功能描述:SYNTHESIZER 制造商:Analog Devices 功能描述:Complete DDS Quadrature 300MSPS TQFP80 |
| AD9854PCB | 制造商:AD 制造商全稱:Analog Devices 功能描述:CMOS 300 MSPS Quadrature Complete DDS |
| AD9856 | 制造商:AD 制造商全稱:Analog Devices 功能描述:CMOS 200 MHz Quadrature Digital Upconverter |
| AD9856/PCB | 制造商:Analog Devices 功能描述:Evaluation Board For Digital Up Converter 56 Pin LFCSP Ep 制造商:Analog Devices 功能描述:DGTL UP CNVRTR 56LFCSP - Bulk |
| AD9856AST | 制造商:Analog Devices 功能描述:Digital Up Converter 48-Pin LQFP Tray 制造商:Analog Devices 功能描述:IC MODULATOR DIGITAL |
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