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| 型號： | AD9782 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 12-Bit, 200 MSPS/500 MSPS TxDAC+ with 2 x /4 x /8 x Interpolation and Signal Processing |
| 中文描述： | 12位，200 MSPS/500 MSPS的TxDAC系列與2 × / 4 × / 8 ×插值與信號處理 |
| 文件頁數(shù)： | 42/52頁 |
| 文件大小： | 1619K |
| 代理商： | AD9782 |
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AD9782
Preliminary Technical Data
OPERATING WITH PLL ENABLED
Note that a specific revision of the AD9782 on the Rev E
Evaluation Board has a nonfunctioning PLL. This revision can
be identified by the xxx.
Rev. PrC | Page 42 of 52
With the AD9782 PLL enabled, the evaluation board clock input
must be run at the data input rate, up to the specified 200 MSPS
limit. The PLL controls the internal clock multiplication and
drives the interpolation filters and digital modulator. The
internal PLL has a VCO in the control loop that is designed to
operate optimally over the 200 MHz to 500 MHz range. The
VCO speed can be calculated as follows:
VCO Speed
=
Input Data Rate
×
PLLMULT
[1,0]
The interpolation rate is set by Bits 6 and 7. With the PLL
enabled, the settings for the interpolation rate, the PLL
multiplier, and the PLL divide are interrelated. The interpolation
rate must meet the following criteria:
Interpolation Rate
=
[Settings of Bits 6, 7
] = [
PLLMULT
÷
PLLDIVIDER
]
Therefore, assuming the input data rate is constant and the
VCO is at optimal speed, if the interpolation rate is increased by
a factor of M, the PLLMULT setting must be decreased by the
same factor M.
With the PLL enabled, DATACLK connector S2 indicates the
lock state of the PLL. A Logic 1 from S2 indicates lock; a Logic 0
indicates the PLL is not currently locked.
ANALOG OUTPUT
The analog output of the AD9782 is accessed via connector S3.
Once all settings are selected and current levels, PLL lock state,
and SPI port functionality are verified, the analog signal at S3
can be viewed. For most of the AD9782’s applications, a
spectrum analyzer is the instrument of choice to verify proper
performance. A typical spectral plot is shown in Figure 74, with
the AD9782 synthesizing a two-tone signal in the default mode
with a 200 MSPS sample rate. A single tone CW signal should
provide output power of approximately +0.5 dBm to the
spectrum analyzer.
If the spectrum does not look correct at this point, the data
input may be violating setup and hold times with respect to the
input clock. To correct this, the user should vary the input data
timing. If this is not possible, SPI Register 02h, Bit 4 can be
inverted. This bit controls the clock edge upon which the data is
latched. If these methods do not correct the spectrum, it is
unlikely that the issue is timing related. This note should then
be reread to verify that all instructions have been followed.
0
10
0
–10
–20
–30
–40
–50
–60
–60
–70
–80
–90
–100
START 100 kHz
STOP 200 MHz
19.9 MHz/
Figure 74. Typical Spectral Plot
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