參數(shù)資料
型號(hào)： AD9782
廠商： Analog Devices, Inc.
英文描述： 12-Bit, 200 MSPS/500 MSPS TxDAC+ with 2 x /4 x /8 x Interpolation and Signal Processing
中文描述： 12位，200 MSPS/500 MSPS的TxDAC系列與2 × / 4 × / 8 ×插值與信號(hào)處理
文件頁(yè)數(shù)： 40/52頁(yè)
文件大小： 1619K
代理商： AD9782
AD9782
Preliminary Technical Data
OPERATING THE AD9782 REV E EVALUATION BOARD
This section helps the user get started with the AD9782
evaluation board. Because it is intended to provide starter
information to power up the board and verify correct operation,
a description of some of the more advanced modes of operation
has been omitted. For a description of the various SPI registers
and the effect they have on the operating modes of the AD9782,
see the Mode Control (via SPI Port) section.
Rev. PrC | Page 40 of 52
POWER SUPPLIES
The AD9782 Rev E Evaluation Board has five power supply
connectors, labeled VDDIN, CVDIN, VDD2IN, VDD3IN, and
AVDIN. The AD9782 itself actually has seven power supply
domains. To reconcile the power supply domains on the chip
with the power supply connectors on the evaluation board, use
Table 38.
Additionally, the DRVDD power supply on the AD9782 is used
to supply power for the digital input bus. DRVDD can be run
from 2.5 V or 3.3 V. On the evaluation board, DRVDD is jumper
selectable by JP1, just to the left of the chip on the evaluation
board. With the jumper set to the 3.3 V position, DRVDD chip
receives its power from VDD3IN. With the jumper set to the
2.5 V position, DRVDD receives its power from AVDIN.
PECL CLOCK DRIVER
The AD9782 system clock is driven from an external source via
connector S1. The AD9782 Evaluation Board includes an
OnSemiconductor MC100EPT22 PECL clock driver. In the
factory, the evaluation board is set to use this PECL driver as a
single-ended-to-differential clock receiver. The PECL driver can
be set to run from 2.5 V from the CVDIN power connector, or
3.3 V from the VDD3IN power connector. This setting is done
via jumper, JP2, situated next to the CVDIN power connector,
and by setting input bias resistors R23 and R4 on the evaluation
board. The factory default is for the PECL driver to be powered
from CVDIN at 2.5 V (R23 = 90.9 , R4 = 115 ). To operate
the PECL driver with a 3.3 V supply, R23 must be replaced with
a 115 resistor and R4 must be replaced with a 115 resistor,
as well as changing the position of JP2. The schematic of the
PECL driver section of the evaluation board is shown below in
Figure 73. A low jitter sine wave can be used as the clock source.
Care must be taken to make sure the clock amplitude does not
exceed the power supply rails for the PECL driver.
0
U2
7
1
2
COND;5
CLKVDDS;8
C32
0.1
μ
F
R23
115
R4
90.9
ACLKX
CLKVDDS
R5
50
R7
50
R6
50
CLKVDDS
MC100EPT22
CLK+
CLK–
Figure 73. PECL Driver on AD9782 Rev E Evaluation Board
Table 38.
Evaluation Board Label
VDDIN
CVDIN
VDD2IN
VDD3IN
AVDIN
PS Domain on Chip
DVDD
CLKVDD
ACVDD and ADVDD
AVDD2
AVDD1
Nominal Power
Supply Voltage (V)
2.5
2.5
2.5
3.3
3.3
Description
SPI port
Clock circuitry
Analog circuitry containing clock and digital interface circuitry
Switching analog circuitry
Analog output circuitry
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