參數(shù)資料
型號(hào): AD9782
廠商: Analog Devices, Inc.
英文描述: 12-Bit, 200 MSPS/500 MSPS TxDAC+ with 2 x /4 x /8 x Interpolation and Signal Processing
中文描述: 12位,200 MSPS/500 MSPS的TxDAC系列與2 × / 4 × / 8 ×插值與信號(hào)處理
文件頁(yè)數(shù): 34/52頁(yè)
文件大?。?/td> 1619K
代理商: AD9782
AD9782
Preliminary Technical Data
POWER DISSIPATION
The AD9782 has seven power supply domains: two 3.3 V analog
domains (AVDD1 and AVDD2), two 2.5 V analog domains
(ADVDD and ACVDD), one 2.5 V clock domain (CLKVDD),
and two digital domains (DVDD, which runs from 2.5 V, and
DRVDD, which can run from 2.5 V or 3.3 V).
Rev. PrC | Page 34 of 52
The current needed for the 3.3 V analog supplies, AVDD1 and
AVDD2, is consistent across speed and varying modes of the
AD9782. Nominally, the current for AVDD1 is 29 mA across all
speeds and modes, while the current for AVDD2 is 20 mA.
The current for the 2.5 V analog supplies and the digital
supplies varies depending on speed and mode of operation.
Figure 55, Figure 56, and Figure 57 show this variation. Note
that CLKVDD, ADVDD, and ACVDD vary with clock speed
and interpolation rate, but not with modulation rate.
0
F
DATA
(MSPS)
250
0
25
50
75
100
125
150
175
200
225
I
0
425
400
375
350
325
300
275
250
225
200
175
150
125
100
75
50
25
2× fs/4
2× fs/8
4× fs/4
4× fs/8
8× fs/4
8× fs/8
Figure 55. DVDD Supply Current vs. Clock Speed, Interpolation, and
Modulation Rates
0
F
DATA
(MSPS)
250
0
25
50
75
100
125
150
175
200
225
I
0
60
50
40
30
20
10
Figure 56. CLKVDD Supply Current vs. Clock Speed and Interpolation Rates
0
F
DATA
(MSPS)
250
0
25
50
75
100
125
150
175
200
225
I
0
30
25
20
15
10
5
Figure 57. ADVDD and ACVDD Supply Current vs. Clock Speed and
Interpolation Rates
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