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| 型號： | AD9782 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 12-Bit, 200 MSPS/500 MSPS TxDAC+ with 2 x /4 x /8 x Interpolation and Signal Processing |
| 中文描述： | 12位，200 MSPS/500 MSPS的TxDAC系列與2 × / 4 × / 8 ×插值與信號處理 |
| 文件頁數(shù)： | 17/52頁 |
| 文件大小： | 1619K |
| 代理商： | AD9782 |
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Preliminary Technical Data
AD9782
SERIAL CONTROL INTERFACE
Rev. PrC | Page 17 of 52
AD9782 SPI
PORT INTERFACE
SDO (PIN 54)
SDIO (PIN 55)
SCLK (PIN 56)
CSB (PIN 57)
0
Figure 29. AD9782 SPI Port Interface
The AD9782 serial port is a flexible, synchronous serial
communications port allowing easy interface to many industry-
standard microcontrollers and microprocessors. The serial I/O
is compatible with most synchronous transfer formats,
including both the Motorola SPI and Intel SSR protocols. The
interface allows read/write access to all registers that configure
the AD9782. Single or multiple byte transfers are supported as
well as MSB first or LSB first transfer formats. The AD9782’s
serial interface port can be configured as a single pin I/O
(SDIO) or two unidirectional pins for in/out (SDIO/SDO).
GENERAL OPERATION OF THE SERIAL INTERFACE
There are two phases to a communication cycle with the
AD9782. Phase 1 is the instruction cycle, which is the writing of
an instruction byte into the AD9782, coincident with the first
eight SCLK rising edges. The instruction byte provides the
AD9782 serial port controller with information regarding the
data transfer cycle, which is Phase 2 of the communication
cycle. The Phase 1 instruction byte defines whether the
upcoming data transfer is read or write, the number of bytes in
the data transfer, and the starting register address for the first
byte of the data transfer. The first eight SCLK rising edges of
each communication cycle are used to write the instruction byte
into the AD9782.
A logic high on the CS pin, followed by a logic low, will reset the
SPI port timing to the initial state of the instruction cycle. This
is true regardless of the present state of the internal registers or
the other signal levels present at the inputs to the SPI port. If the
SPI port is in the midst of an instruction cycle or a data transfer
cycle, none of the present data will be written.
The remaining SCLK edges are for Phase 2 of the
communication cycle. Phase 2 is the actual data transfer
between the AD9782 and the system controller. Phase 2 of the
communication cycle is a transfer of 1, 2, 3, or 4 data bytes as
determined by the instruction byte. Normally, using one
multibyte transfer is the preferred method. However, single byte
data transfers are useful to reduce CPU overhead when register
access requires one byte only. Registers change immediately
upon writing to the last bit of each transfer byte.
INSTRUCTION BYTE
The instruction byte contains the following information:
Table 8.
N1
N2
Description
0
0
Transfer 1 Byte
0
1
Transfer 2 Bytes
1
0
Transfer 3 Bytes
1
1
Transfer 4 Bytes
R/W,
Bit 7 of the instruction byte, determines whether a read or
a write data transfer will occur after the instruction byte write.
Logic high indicates read operation. Logic 0 indicates a write
operation. N1, N0, Bits 6 and 5 of the instruction byte,
determine the number of bytes to be transferred during the data
transfer cycle. The bit decodes are shown in the following table:
Table 9.
MSB
17
16
15
14
R/W
N1
N0
A4
13
A3
12
A2
11
A1
LSB
10
A0
A4, A3, A2, A1, A0
, Bits 4, 3, 2, 1, 0 of the instruction byte,
determine which register is accessed during the data transfer
portion of the communications cycle. For multibyte transfers,
this address is the starting byte address. The remaining register
addresses are generated by the AD9782.
SERIAL INTERFACE PORT PIN DESCRIPTIONS
SCLK—Serial Clock
. The serial clock pin is used to
synchronize data to and from the AD9782 and to run the
internal state machines. SCLK’s maximum frequency is 15 MHz.
All data input to the AD9782 is registered on the rising edge of
SCLK. All data is driven out of the AD9782 on the falling edge
of SCLK.
CSB—Chip Select
. Active low input starts and gates a
communication cycle. It allows more than one device to be used
on the same serial communications lines. The SDO and SDIO
pins will go to a high impedance state when this input is high.
Chip select should stay low during the entire communication
cycle.
SDIO—Serial Data I/O
. Data is always written into the
AD9782 on this pin. However, this pin can be used as a
bidirectional data line. The configuration of this pin is
controlled by Bit 7 of register address 00h. The default is
Logic 0, which configures the SDIO pin as unidirectional.
SDO—Serial Data Out
. Data is read from this pin for protocols
that use separate lines for transmitting and receiving data. In the
case where the AD9782 operates in a single bidirectional I/O
mode, this pin does not output data and is set to a high
impedance state.
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