- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄373967 > AD9782 (Analog Devices, Inc.) 12-Bit, 200 MSPS/500 MSPS TxDAC+ with 2 x /4 x /8 x Interpolation and Signal Processing PDF資料下載
參數(shù)資料
| 型號： | AD9782 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 12-Bit, 200 MSPS/500 MSPS TxDAC+ with 2 x /4 x /8 x Interpolation and Signal Processing |
| 中文描述： | 12位，200 MSPS/500 MSPS的TxDAC系列與2 × / 4 × / 8 ×插值與信號處理 |
| 文件頁數(shù)： | 27/52頁 |
| 文件大小： | 1619K |
| 代理商： | AD9782 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁當前第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁
Preliminary Technical Data
AD9782
Figure 44 shows the same conditions, with DATAADJ now set
to 0001, thus moving DATACLK to the right in the plot. This
indicates that it occurs one DACCLK cycle after it did in
Figure 42. Now the latching edge of DACCLK moves forward in
time one cycle.
Rev. PrC | Page 27 of 52
0
RISING EDGE OF DATACLK
CONCURRENT WITH
LATCHING EDGE OF DACCLK
DATA TRANSITION
DACCLK
LATCHING EDGE
Figure 44. DATAADJ = 0001
INTERPOLATION MODES
Table 27.
INTERP[1]
0
0
1
1
INTERP[0]
0
1
0
1
Mode
No Interpolation
×2 Interpolation
×4 Interpolation
×8 Interpolation
Interpolation is the process of increasing the number of points
in a time domain waveform by approximating points between
the input data points; on a uniform time grid, this produces a
higher output data rate. Applied to an interpolation DAC, a
digital interpolation filter is used to approximate the interpo-
lated points, having an output data rate increased by the
interpolation factor. Interpolation filter responses are achieved
by cascading individual digital filter banks, whose filter
coefficients are given in Table 1; filter responses are shown in
Figure 34.
The digital filter’s frequency domain response exhibits
symmetry about half the output data rate and dc. It will cause
images of the input data to be shaped by the interpolation
filter’s frequency response. This has the advantage of causing
input data images, which fall in the stop band of the digital filter
to be rejected by the stop-band attenuation of the interpolation
filter; input data images falling in the interpolation filter’s pass-
band will be passed. In band-limited applications, the images at
the output of the DAC must be limited by an analog reconstruc-
tion filter. The complexity of the analog reconstruction filter is
determined by the proximity of the closest image to the
required signal band. Higher interpolation rates yield larger
stop-band regions, suppressing more input images and resulting
in a much relaxed analog reconstruction filter.
A DAC shapes its output with a sinc function, having a null at
the sampling frequency of the DAC. The higher the DAC sam-
pling rate compared to the input signal bandwidth, the less the
DAC sinc function will shape the output. Figure 45 shows the
interpolation filters of the AD9782 under different interpolation
rates, normalized to the input data rate, f
SIN
. The higher the
interpolation rate the more input data images fall in the
interpolation filter stop band and are rejected; the band-width
between passed images is larger with higher interpolation
factors. The sinc function shaping is also reduced with a higher
interpolation factor.
Table 28.
Mode
No Interpolation
×2 Interpolation
×4 Interpolation
×8 Interpolation
Sinc Shaping
at 0.43f
SIN
(dB)
–2.8241
–0.6708
–0.1657
–0.0413
Bandwidth to First Image
f
SIN
2f
SIN
4f
SIN
8f
SIN
相關PDF資料 |
PDF描述 |
|---|---|
| AD9786BSV | 16-Bit, 200 MSPS/500 MSPS TxDAC+ with 2】/4】/8】 Interpolation and Signal Processing |
| AD9786 | 16-Bit, 200 MSPS/500 MSPS TxDAC+ with 2】/4】/8】 Interpolation and Signal Processing |
| AD9786BSVRL | 16-Bit, 200 MSPS/500 MSPS TxDAC+ with 2】/4】/8】 Interpolation and Signal Processing |
| AD9801 | CCD Signal Processor For Electronic Cameras(用于電子照相機的CCD信號處理器) |
| AD9802JST | Silver Mica Capacitor; Capacitance:10pF; Capacitance Tolerance: 5%; Series:CD17; Voltage Rating:500VDC; Capacitor Dielectric Material:Mica; Termination:Radial Leaded; Lead Pitch:5.9mm; Leaded Process Compatible:Yes RoHS Compliant: Yes |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AD9783 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual 12-/14-/16-Bit, LVDS Interface, 500 MSPS DACs |
| AD9783BCPZ | 功能描述:IC DAC 16BT 500MSPS LVDS 72LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉換器 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:50 系列:- 設置時間:4µs 位數(shù):12 數(shù)據(jù)接口:串行 轉換器數(shù)目:2 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:8-TSSOP，8-MSOP（0.118"，3.00mm 寬） 供應商設備封裝:8-uMAX 包裝:管件 輸出數(shù)目和類型:2 電壓，單極 采樣率（每秒）:* 產(chǎn)品目錄頁面:1398 (CN2011-ZH PDF) |
| AD9783BCPZRL | 功能描述:IC DAC 16BT 500MSPS LVDS 72LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉換器 系列:- 產(chǎn)品培訓模塊:Data Converter Fundamentals DAC Architectures 標準包裝:750 系列:- 設置時間:7µs 位數(shù):16 數(shù)據(jù)接口:并聯(lián) 轉換器數(shù)目:1 電壓電源:雙 ± 功率耗散（最大）:100mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-LCC（J 形引線） 供應商設備封裝:28-PLCC（11.51x11.51） 包裝:帶卷 (TR) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:143k |
| AD9783-DPG2-EBZ | 功能描述:BOARD EVAL FOR AD9783 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 數(shù)模轉換器 (DAC) 系列:* 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- DAC 的數(shù)量:4 位數(shù):12 采樣率（每秒）:- 數(shù)據(jù)接口:串行，SPI? 設置時間:3µs DAC 型:電流/電壓 工作溫度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581 |
| AD9783-DUAL-EBZ | 制造商:Analog Devices 功能描述:DUAL 16B, 500 MSPS LVDS DAC - Boxed Product (Development Kits) |
發(fā)布緊急采購，3分鐘左右您將得到回復。