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參數(shù)資料
| 型號： | AD9782 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 12-Bit, 200 MSPS/500 MSPS TxDAC+ with 2 x /4 x /8 x Interpolation and Signal Processing |
| 中文描述： | 12位，200 MSPS/500 MSPS的TxDAC系列與2 × / 4 × / 8 ×插值與信號處理 |
| 文件頁數(shù)： | 41/52頁 |
| 文件大?。?/td> | 1619K |
| 代理商： | AD9782 |
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Preliminary Technical Data
AD9782
DATA INPUTS
Digital data inputs to the AD9782 are accessed on the
evaluation board through connectors J1 and J2. These are 40 pin
right angle connectors that are intended to be used with
standard ribbon cable connectors. The input levels should be
either 3.3 V or 2.5 V CMOS, depending on the setting of the
DRVDD jumper JP1. The data format is selectable through
Register 02h, Bit 7 (DATAFMT). With this bit set to a default 0,
the AD9782 assumes that the input data is in twos complement
format. With this bit set to 1, data should be input in offset
binary format.
Rev. PrC | Page 41 of 52
When the evaluation board is first powered up and the clock
and data are running, it is recommended that the proper
operating current is verified. Depress reset switch SW1 to
ensure that the AD9782 is in the default mode. The default
mode for the AD9782 is for the internal PLL to be disabled, and
the interpolation set to 1×. The modulator is turned off in the
default mode. The nominal operating currents for the
evaluation board in the power-up default mode are shown in
Table 39.
Additionally, the DRVDD power supply on the AD9782 is used
to supply power for the digital input bus. DRVDD can be run
from 2.5 V or 3.3 V. On the evaluation board, DRVDD is jumper
selectable by JP1, just to the left of the chip on the evaluation
board. With the jumper set to the 3.3 V position, DRVDD chip
receives its power from VDD3IN. With the jumper set to the
2.5 V position, DRVDD receives its power from AVDIN.
Table 39. Nominal Operating Currents in Power-Up Default Mode
SPI PORT
SW1 is a hard reset switch that sets the AD9782 to its default
state. It should be used every time the AD9782 power supply is
cycled or the clock is interrupted, or if new data is to be written
via the SPI port. For a description of the various SPI registers
and the effect they have on the operating modes of the AD9782,
see the Mode Control (via SPI Port) section. Set the SPI
software to read back data from the AD9782 and verify that
when the software is run, the expected values are read back.
OPERATING WITH PLL DISABLED
The SPI registers referenced in this section are shown in
Table 40.
With the PLL disabled, the evaluation board clock input must
be run at the intended DAC sample rate, up to the specified
limit of 500 MSPS. At the same time, the interpolation rate
should be set so the input data rate does not exceed the 200
MSPS limit. In the default mode with the PLL disabled, the
DATACLK signal from the AD9782 is available at connector S2.
The rate of this clock is the system clock applied at S1, divided
by the interpolation rate. DATACLK can be used to synchronize
the external data into the AD9782.
Nominal Current @ Speed (mA)
100 MSPS
49
83
4
30
27
Evaluation Board Power Supply
VDDIN
CVDIN
VDD2IN
VDD3IN
AVDIN
Table 40. SPI Registers
Register
01h
04h
50 MSPS
24
79
1
30
27
150 MSPS
74
87
6
30
27
200 MSPS
99
92
8
30
27
Bit 7
INTERP[1]
PLLON
Bit 6
INTERP[0]
PLLMULT[1]
Bit 5
PLLMULT[0]
Bit 4
PLLDIV[1]
Bit 3
PLLDIV[0]
Bit 0
PLOCKEXT
Interpolation Rate
Bit 6
0
1
0
1
PLL Multiplier
Bit 5
0
1
0
1
PLL Divider
Bit 3
0
1
0
1
Bit 7
0
0
1
1
Rate
1×
2×
4×
8×
Bit 6
0
0
1
1
Mult
2×
4×
8×
16×
Bit 4
0
0
1
1
Div
÷1
÷2
÷4
÷8
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