Input High Voltage, V
參數(shù)資料
型號(hào): AD7195BCPZ-RL7
廠商: Analog Devices Inc
文件頁數(shù): 42/45頁
文件大?。?/td> 0K
描述: IC AFE 24BIT 4.8K 32LFSP
設(shè)計(jì)資源: Precision Weigh Scale Design Using AD7195 with Internal PGA and AC Excitation (CN0155)
標(biāo)準(zhǔn)包裝: 1,500
位數(shù): 24
通道數(shù): 4
電壓 - 電源,模擬: 4.75 V ~ 5.25 V
電壓 - 電源,數(shù)字: 2.7 V ~ 5.25 V
封裝/外殼: 32-WFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 32-LFCSP-WQ(5x5)
包裝: 帶卷 (TR)
AD7195
Rev. 0 | Page 5 of 44
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments1
LOGIC INPUTS
Input High Voltage, VINH2
2
V
Input Low Voltage, VINL2
0.8
V
Hysteresis2
0.1
0.25
V
Input Currents
10
+10
μA
LOGIC OUTPUT (DOUT/RDY)
Output High Voltage, VOH2
DVDD 0.6
V
DVDD = 3 V, ISOURCE = 100 μA
Output Low Voltage, VOL2
0.4
V
DVDD = 3 V, ISINK = 100 μA
Output High Voltage, VOH2
4
V
DVDD = 5 V, ISOURCE = 200 μA
Output Low Voltage, VOL2
0.4
V
DVDD = 5 V, ISINK = 1.6 mA
Floating-State Leakage
Current
10
+10
μA
Floating-State Output
Capacitance
10
pF
Data Output Coding
Offset binary
SYSTEM CALIBRATION2
Full-Scale Calibration Limit
1.05 × FS
V
Zero-Scale Calibration Limit
1.05 × FS
V
Input Span
0.8 × FS
2.1 × FS
V
POWER REQUIREMENTS7
Power Supply Voltage
AVDD AGND
4.75
5.25
V
DVDD DGND
2.7
5.25
V
Power Supply Currents
AIDD Current
0.85
1
mA
gain = 1, buffer off
1.1
1.3
mA
gain = 1, buffer on
3.5
4.5
mA
gain = 8, buffer off
4
5
mA
gain = 8, buffer on
5
6.4
mA
gain = 16 to 128, buffer off
5.5
6.9
mA
gain = 16 to 128, buffer on
DIDD Current
0.35
0.4
mA
DVDD = 3 V
0.5
0.6
mA
DVDD = 5 V
1.5
mA
External crystal used
IDD (Power-Down Mode)
2
μA
1 Temperature range: 40°C to +105°C.
2 Specification is not production tested, but is supported by characterization data at initial product release.
3 FS is the decimal equivalent of Bit FS9 to Bit FS0 in the mode register.
4 Following a system or internal zero-scale calibration, the offset error is in the order of the noise for the programmed gain and output data rate selected. A system full-
scale calibration reduces the gain error to the order of the noise for the programmed gain and output data rate.
5 The analog inputs are configured for differential mode.
6 REJ60 is a bit in the mode register. When the output data rate is set to 50 Hz, setting REJ60 to 1 places a notch at 60 Hz, allowing simultaneous 50 Hz/60 Hz rejection.
7 Digital inputs equal to DVDD or DGND.
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