- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1980 > AD7195BCPZ-RL7 (Analog Devices Inc)IC AFE 24BIT 4.8K 32LFSP PDF資料下載
參數(shù)資料
| 型號： | AD7195BCPZ-RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 24/45頁 |
| 文件大小： | 0K |
| 描述： | IC AFE 24BIT 4.8K 32LFSP |
| 設計資源： | Precision Weigh Scale Design Using AD7195 with Internal PGA and AC Excitation (CN0155) |
| 標準包裝： | 1,500 |
| 位數(shù)： | 24 |
| 通道數(shù)： | 4 |
| 電壓 - 電源，模擬： | 4.75 V ~ 5.25 V |
| 電壓 - 電源，數(shù)字： | 2.7 V ~ 5.25 V |
| 封裝/外殼： | 32-WFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 32-LFCSP-WQ（5x5） |
| 包裝： | 帶卷 (TR) |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁當前第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁
AD7195
Rev. 0 | Page 29 of 44
The serial interface can operate in 3-wire mode by tying CS low.
In this case, the SCLK, DIN, and DOUT/RDY lines are used to
communicate with the AD7195. The end of the conversion can
be monitored using the RDY bit or pin. This scheme is suitable
for interfacing to microcontrollers. If CS is required as a decoding
signal, it can be generated from a port pin. For microcontroller
interfaces, it is recommended that SCLK idle high between data
transfers.
The AD7195 can be operated with CS used as a frame synchro-
nization signal. This scheme is useful for DSP interfaces. In this
case, the first bit (MSB) is effectively clocked out by CS because
CS normally occurs after the falling edge of SCLK in DSPs. The
SCLK can continue to run between data transfers, provided the
timing numbers are obeyed.
The serial interface can be reset by writing a series of 1s to the
DIN input. If a Logic 1 is written to the AD7195 DIN line for
at least 40 serial clock cycles, the serial interface is reset. This
ensures that the interface can be reset to a known state if the
interface gets lost due to a software error or some glitch in the
system. Reset returns the interface to the state in which it expects
a write to the communications register. This operation resets the
contents of all registers to their power-on values. Following a
reset, the user should allow a period of 500 μs before addressing
the serial interface.
The AD7195 can be configured to continuously convert or to
Single Conversion Mode
In single conversion mode, the AD7195 is placed in power-
down mode after conversions. When a single conversion is
initiated by setting MD2, MD1, and MD0 to 0, 0, 1, respectively,
in the mode register, the AD7195 powers up, performs a single
conversion, and then returns to power-down mode. The on-
chip oscillator requires 1 ms, approximately, to power up.
DOUT/RDY goes low to indicate the completion of a conver-
sion. When the data-word has been read from the data register,
DOUT/RDY goes high. If CS is low, DOUT/RDY remains high
until another conversion is initiated and completed. The data
register can be read several times, if required, even when
DOUT/RDY has gone high.
If several channels are enabled, the ADC sequences through the
enabled channels and performs a conversion on each channel.
When a conversion is started, DOUT/RDY goes high and
remains high until a valid conversion is available. As soon as
the conversion is available, DOUT/RDY goes low. The ADC
then selects the next channel and begins a conversion. The user
can read the present conversion while the next conversion is
being performed. As soon as the next conversion is complete,
the data register is updated; therefore, the user has a limited
period in which to read the conversion. When the ADC has
performed a single conversion on each of the selected channels,
it returns to power-down mode.
If the DAT_STA bit in the mode register is set to 1, the contents
of the status register are output along with the conversion each
time that the data read is performed. The four LSBs of the status
register indicate the channel to which the conversion corresponds.
DIN
SCLK
DOUT/RDY
CS
0x08
0x58
DATA
0x280060
0
87
71-
029
Figure 21. Single Conversion
相關PDF資料 |
PDF描述 |
|---|---|
| AD7225BQ | IC DAC 8BIT QUAD W/AMP 24-CDIP |
| AD7226BQ | IC DAC 8BIT QUAD W/AMP 20-CDIP |
| AD7228CQ | IC DAC 8BIT OCTAL W/AMP 24-CDIP |
| AD7233BNZ | IC DAC 12BIT SRL W/AMP 8PDIP |
| AD7243BQ | IC DAC 12BIT W/AMP W/REF 16-CDIP |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AD71L | 制造商:Johnson Components 功能描述:ADAPT - Bulk |
| AD72 | 制造商:Distributed By MCM 功能描述:REFRIGERATR DOOR GASKET DIRECT |
| AD720 | 制造商:AD 制造商全稱:Analog Devices 功能描述:RGB to NTSC/PAL Encoders |
| AD720-00E | 功能描述:SENSOR MAG SW 28G STANDRD 8-MSOP 制造商:nve corp/sensor products 系列:AD 包裝:管件 零件狀態(tài):有效 功能:全極開關 技術:霍爾效應 極化:任意一種 感應范圍:±3.4mT 跳閘，±1.4mT 釋放 測試條件:-40°C ~ 125°C 電壓 - 電源:4.5 V ~ 30 V 電流 - 電源（最大值）:4.5mA 電流 - 輸出（最大值）:20mA 輸出類型:開路集電極 特性:- 工作溫度:-40°C ~ 125°C（TA） 封裝/外殼:8-TSSOP，8-MSOP（0.118"，3.00mm 寬） 供應商器件封裝:8-MSOP 標準包裝:1,000 |
| AD720-02E | 功能描述:SENSOR MAG SW 28G STANDARD 8SOIC 制造商:nve corp/sensor products 系列:AD 包裝:管件 零件狀態(tài):有效 功能:全極開關 技術:霍爾效應 極化:任意一種 感應范圍:±3.4mT 跳閘，±1.4mT 釋放 測試條件:-40°C ~ 125°C 電壓 - 電源:4.5 V ~ 30 V 電流 - 電源（最大值）:4.5mA 電流 - 輸出（最大值）:20mA 輸出類型:開路集電極 特性:- 工作溫度:-40°C ~ 125°C（TA） 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應商器件封裝:8-SOIC 標準包裝:1,000 |
發(fā)布緊急采購，3分鐘左右您將得到回復。