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參數(shù)資料
| 型號： | AD7195BCPZ-RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 22/45頁 |
| 文件大小： | 0K |
| 描述： | IC AFE 24BIT 4.8K 32LFSP |
| 設(shè)計(jì)資源： | Precision Weigh Scale Design Using AD7195 with Internal PGA and AC Excitation (CN0155) |
| 標(biāo)準(zhǔn)包裝： | 1,500 |
| 位數(shù)： | 24 |
| 通道數(shù)： | 4 |
| 電壓 - 電源，模擬： | 4.75 V ~ 5.25 V |
| 電壓 - 電源，數(shù)字： | 2.7 V ~ 5.25 V |
| 封裝/外殼： | 32-WFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 32-LFCSP-WQ（5x5） |
| 包裝： | 帶卷 (TR) |
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AD7195
Rev. 0 | Page 28 of 44
in ac excitation where resistor divider arrangements on the
reference input add to the settling time associated with the
switching.
When several channels are enabled, the ADC must allow the
complete settling time to generate a valid conversion each time
that the channel is changed. The AD7195 takes care of this:
when a channel is selected, the modulator and filter are reset,
and the RDY pin is taken high. The AD7195 then allows the
complete settling time to generate the first conversion. RDY
goes low only when a valid conversion is available. The AD7195
then selects the next enabled channel and converts on that
channel. The user can then read the data register while the
ADC is performing the conversion on the next channel.
When the ACX bit in the configuration register is set to 0,
the digital outputs ACX1 and ACX2 are high, while outputs
ACX2 and ACX1 are low. Therefore, the bridge is dc excited
with the T2 and T4 transistors turned on and the T1 and T3
transistors turned off. When the AD7195 is in power-down
mode, outputs ACX1 and ACX2 are low and outputs ACX1
and ACX2 are high so that the excitation voltage is discon-
nected from the bridge.
The time required to read a valid conversion from all enabled
channels is equal to
CHANNEL SEQUENCER
tSETTLE × number of enabled channels
The AD7195 includes a channel sequencer, which simplifies
communications with the device in multichannel applications.
The sequencer also optimizes the channel throughput of the
device because the sequencer switches channels at the optimum
rate rather than waiting for instructions via the SPI interface.
For example, if the sinc4 filter is selected, chop is disabled, and
zero latency is disabled, the settling time for each channel is
equal to
tSETTLE = 4/fADC
Bit CH0 to Bit CH7 in the configuration register are used to
enable the required channels. In continuous conversion mode,
the ADC selects each of the enabled channels in sequence and
performs a conversion on the channel. The RDY pin goes low
when a valid conversion is available on each channel. When
several channels are enabled, the contents of the status register
should be attached to the 24-bit word so that the user can
identify the channel that corresponds to each conversion. To
attach the status register value to the conversion, Bit DAT_STA
in the mode register should be set to 1.
where fADC is the output data rate when continuously converting
on a single channel. The time required to sample N channels is
4/(fADC× N)
RDY
CONVERSIONS
CHANNEL A
CHANNEL B
1/fADC
CHANNEL C
08771-
028
Figure 20. Channel Sequencer
The DOUT/RDY pin functions as a data ready signal also; the
line goes low when a new data-word is available in the output
register. It is reset high when a read operation from the data
register is complete. It also goes high prior to the updating of the
data register to indicate when not to read from the device to
ensure that a data read is not attempted while the register is being
updated. CS is used to select a device. It can be used to decode the
AD7195 in systems where several components are connected to
the serial bus.
DIGITAL INTERFACE
As indicated in the On-Chip Registers section, the program-
mable functions of the AD7195 are controlled using a set of
on-chip registers. Data is written to these registers via the serial
interface of the part. Read access to the on-chip registers is also
provided by this interface. All communication with the part must
start with a write to the communications register. After power-on
or reset, the device expects a write to its communications register.
The data written to this register determines whether the next oper-
ation is a read operation or a write operation and determines to
which register this read or write operation occurs. Therefore,
write access to any of the other registers on the part begins with
a write operation to the communications register, followed by a
write to the selected register. A read operation from any other
register (except when continuous read mode is selected) starts
with a write to the communications register, followed by a read
operation from the selected register.
AD7195, with CS being used to decode the part.
shows
the timing for a read operation from the output shift register of
the AD7195, and
shows the timing for a write operation
to the input shift register.
It is possible to read the same word from the data register several
times even though the DOUT/RDY line returns high after the
first read operation. However, care must be taken to ensure that
the read operations are completed before the next output update
occurs. In continuous read mode, the data register can be read
only once.
The serial interface of the AD7195 consists of four signals: CS,
DIN, SCLK, and DOUT/RDY. The DIN line is used to transfer
data into the on-chip registers and DOUT/RDY is used for
accessing data from the on-chip registers. SCLK is the serial
clock input for the device, and all data transfers (either on DIN
or DOUT/RDY) occur with respect to the SCLK signal.
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