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參數(shù)資料
| 型號(hào)： | AD7195BCPZ-RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 16/45頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC AFE 24BIT 4.8K 32LFSP |
| 設(shè)計(jì)資源： | Precision Weigh Scale Design Using AD7195 with Internal PGA and AC Excitation (CN0155) |
| 標(biāo)準(zhǔn)包裝： | 1,500 |
| 位數(shù)： | 24 |
| 通道數(shù)： | 4 |
| 電壓 - 電源，模擬： | 4.75 V ~ 5.25 V |
| 電壓 - 電源，數(shù)字： | 2.7 V ~ 5.25 V |
| 封裝/外殼： | 32-WFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 32-LFCSP-WQ（5x5） |
| 包裝： | 帶卷 (TR) |
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AD7195
Rev. 0 | Page 22 of 44
Table 24. Configuration Register Bit Designations
Bit Location
Bit Name
Description
CON23
CHOP
Chop enable bit. When the CHOP bit is cleared, chop is disabled. When the CHOP bit is set, chop is
enabled. When chop is enabled, the offset and offset drift of the ADC are continuously removed.
However, this increases the conversion time and settling time of the ADC. For example, when FS = 96
decimal and the sinc4 filter is selected, the conversion time with chop enabled equals 80 ms and the
settling time equals 160 ms. With chop disabled, higher conversion rates are allowed. For an FS word
of 96 decimal and the sinc4 filter selected, the conversion time is 20 ms and the settling time is 80 ms.
However, at low gains, periodic calibrations may be required to remove the offset and offset drift.
When ax excitation is enabled, chop must be enabled also.
CON22
ACX
AC excitation enable bit. If the signal source to the AD7195 is ac excited, this bit must be set to 1. For
dc-excited inputs, this bit must be 0. With the ACX bit at 1, the AD7195 assumes that the voltage at the
AIN(+)/AIN(–) and REFIN(+)/REFIN(–) input terminals are reversed on alternate input sampling cycles
(that is, chopped). Note that when the AD7195 is performing internal zero-scale or full-scale calibra-
tions, the ACX bit is treated as a 0, that is, the device performs these self-calibrations with dc excitation.
TheBitCHOP must be set to 1 when ac excitation is enabled.
CON21 to CON16
0
These bits must be programmed with a Logic 0 for correct operation.
CON15 to CON8
CH7 to CH0
Channel select bits. These bits are used to select which channels are enabled on the AD7195 (see Table 25).
Several channels can be selected, and the AD7195 automatically sequences them. The conversion on
each channel requires the complete settling time. When performing calibrations or when accessing the
calibration registers, only one channel can be selected.
CON7
BURN
When this bit is set to 1, the 500 nA current sources in the signal path are enabled. When BURN = 0, the
burnout currents are disabled. The burnout currents can be enabled only when the buffer is active and
when chop is disabled.
CON6
REFDET
Enables the reference detect function. When set, the NOREF bit in the status register indicates when the
external reference being used by the ADC is open circuit or less than 0.6 V maximum. The reference
detect circuitry operates only when the ADC is active.
CON5
0
This bit must be programmed with a Logic 0 for correct operation.
CON4
BUF
Enables the buffer on the analog inputs. If cleared, the analog inputs are unbuffered, lowering the
power consumption of the device. If this bit is set, the analog inputs are buffered, allowing the user to
place source impedances on the front end without contributing gain errors to the system. With the
buffer disabled, the voltage on the analog input pins can be from 50 mV below AGND to 50 mV above
AVDD. When the buffer is enabled, it requires some headroom; therefore, the voltage on any input pin
must be limited to 250 mV within the power supply rails.
CON3
U/B
Polarity select bit. When this bit is set, unipolar operation is selected. When this bit is cleared, bipolar
operation is selected.
CON2 to CON0
G2 to G0
Gain select bits. These bits are written by the user to select the ADC input range as follows:
G2
G1
G0
Gain
ADC Input Range (5 V Reference)
0
1
±5 V
0
1
Reserved
0
1
0
Reserved
0
1
8
±625 mV
1
0
16
±312.5 mV
1
0
1
32
±156.2 mV
1
0
64
±78.125 mV
1
128
±39.06 mV
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