fADC = 1/t
參數(shù)資料
型號(hào)： AD7195BCPZ-RL7
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 32/45頁(yè)
文件大?。?/td> 0K
描述： IC AFE 24BIT 4.8K 32LFSP
設(shè)計(jì)資源： Precision Weigh Scale Design Using AD7195 with Internal PGA and AC Excitation (CN0155)
標(biāo)準(zhǔn)包裝： 1,500
位數(shù)： 24
通道數(shù)： 4
電壓 - 電源，模擬： 4.75 V ~ 5.25 V
電壓 - 電源，數(shù)字： 2.7 V ~ 5.25 V
封裝/外殼： 32-WFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 32-LFCSP-WQ（5x5）
包裝： 帶卷 (TR)
AD7195
Rev. 0 | Page 37 of 44
The output data rate equals
fADC = 1/tSETTLE = fCLK/(3 × 1024 × FS[9:0])
where:
fADC is the output data rate.
fCLK is the master clock (4.92 MHz nominal).
FS[9:0] is the decimal equivalent of Bit FS9 to Bit FS0 in the
mode register.
When the analog input is constant or a channel change occurs,
valid conversions are available at a constant output data rate.
When conversions are being performed on a single channel and
a step change occurs on the analog input, the ADC continues to
output fully settled conversions if the step change is synchronized
with the conversion process. If the step change is asynchronous,
one conversion is output from the ADC that is not completely
settled (see Figure 35).
ANALOG
INPUT
ADC
OUTPUT
FULLY
SETTLED
1/
fADC
08
77
1-
04
7
Figure 35. Sinc3 Zero Latency Operation
Table 32 provides examples of output data rates and the corres-
ponding FS values.
Table 32. Examples of Output Data Rates and the
Corresponding Settling Time (Zero Latency)
FS[9:0]
Output Data Rate (Hz)
Settling Time (ms)
480
3.3
300
96
16.7
60
80
20
50
Sinc3 50 Hz/60 Hz Rejection
Figure 36 show the frequency response of the sinc3 filter when
FS[9:0] is set to 96 and the master clock equals 4.92 MHz. The
output data rate is equal to 50 Hz when zero latency is disabled
and 16.7 Hz when zero latency is enabled. The sinc3 filter gives
50 Hz ± 1 Hz rejection of 95 dB minimum for a stable master clock.
–120
–110
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
25
50
75
100
125
150
FREQUENCY (Hz)
F
IL
T
E
R
GA
IN
(d
B
)
08
77
1-
0
48
Figure 36. Sinc3 Filter Response (FS[9:0] = 96)
When FS[9:0] is set to 80 and the master clock equals
4.92 MHz, 60 Hz rejection is achieved (see Figure 37). The
output data rate is equal to 60 Hz when zero latency is disabled
and 20 Hz when zero latency is enabled. The sinc3 filter has
rejection of 95 dB minimum at 60 Hz ± 1 Hz, assuming a stable
master clock.
–120
–110
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
30
60
90
120
150
FREQUENCY (Hz)
FI
L
T
E
R
GA
IN
(
d
B
)
08
77
1-
04
9
Figure 37. Sinc3 Filter Response (FS[9:0] = 80)
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