參數(shù)資料
型號： AD7195BCPZ-RL7
廠商： Analog Devices Inc
文件頁數(shù)： 17/45頁
文件大?。?/td> 0K
描述： IC AFE 24BIT 4.8K 32LFSP
設(shè)計資源： Precision Weigh Scale Design Using AD7195 with Internal PGA and AC Excitation (CN0155)
標(biāo)準(zhǔn)包裝： 1,500
位數(shù)： 24
通道數(shù)： 4
電壓 - 電源，模擬： 4.75 V ~ 5.25 V
電壓 - 電源，數(shù)字： 2.7 V ~ 5.25 V
封裝/外殼： 32-WFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 32-LFCSP-WQ（5x5）
包裝： 帶卷 (TR)
AD7195
Rev. 0 | Page 23 of 44
Table 25. Channel Selection
Channel Enable Bits in the Configuration Register
Channel Enabled
Status Register
Bits CHD[2:0]
Calibration
Register Pair
CH7
CH6
CH5
CH4
CH3
CH2
CH1
CH0
Positive Input
AIN(+)
Negative Input
AIN()
1
AIN1
AIN2
000
0
1
AIN3
AIN4
001
1
Temperature sensor
010
None
1
AIN2
011
0
1
AIN1
AINCOM
100
0
1
AIN2
AINCOM
101
1
AIN3
AINCOM
110
2
1
AIN4
AINCOM
111
3
DATA REGISTER
(RS2, RS1, RS0 = 0, 1, 1; Power-On/Reset = 0x000000)
The conversion result from the ADC is stored in this data register. This is a read-only, 24-bit register. On completion of a read operation
from this register, the RDY pin/bit is set. When the DAT_STA bit in the mode register is set to 1, the contents of the status register are
appended to each 24-bit conversion. This is advisable when several analog input channels are enabled because the three LSBs of the status
register (CHD2 to CHD0) identify the channel from which the conversion originated.
ID REGISTER
(RS2, RS1, RS0 = 1, 0, 0; Power-On/Reset = 0xA6)
The identification number for the AD7195 is stored in the ID register. This is a read-only register.
GPOCON REGISTER
(RS2, RS1, RS0 = 1, 0, 1; Power-On/Reset = 0x00)
The GPOCON register is an 8-bit register from which data can be read or to which data can be written. This register is used to enable the
general-purpose digital outputs.
Table 26 outlines the bit designations for the GPOCON register. GP0 through GP7 indicate the bit locations. GP denotes that the bits are
in the GPOCON register. GP7 denotes the first bit of the data stream. The number in parentheses indicates the power-on/reset default
status of that bit.
GP7
GP6
GP5
GP4
GP3
GP2
GP1
GP0
0
BPDSW(0)
0
Table 26. Register Bit Designations
Bit Location
Bit Name
Description
GP7
0
This bit must be programmed with a Logic 0 for correct operation.
GP 6
BPDSW
Bridge power-down switch control bit. This bit is set by the user to close the bridge power-down switch
BPDSW to AGND. The switch can sink up to 30 mA. The bit is cleared by the user to open the bridge power-
down switch. When the ADC is placed in power-down mode, the bridge power-down switch remains active.
GP5 to GP0
0
These bits must be programmed with a Logic 0 for correct operation.
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